Abstract: An electronic device includes a substrate, a transistor disposed on the substrate, an electrode disposed on the substrate and coupled to the transistor, and a plurality of electronic units disposed on the substrate and coupled to the electrode. The transistor is used to align the plurality of electronic units when the plurality of electronic units are in an alignment mode, and the transistor is turned off when the plurality of electronic units are in an operating mode.

Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.

Abstract: A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.

Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.

Abstract: A cycling sport performance level analysis system includes an artificial intelligence classification analysis module, a bicycle apparatus, a classification knowledge rule module and a cyclist information module. The classification knowledge rule module transmits a classification test task rule including a track information to the artificial intelligence classification analysis module and the bicycle apparatus. The bicycle apparatus performs the classification test task rule and collects a sport sensing information which is sensed to transmit the sport sensing information to the artificial intelligence classification analysis module. The cyclist information module transmits a cyclist basic information and a track historical riding information to the artificial intelligence classification analysis module.

Abstract: The present invention relates to pharmaceutical compositions of the c-Met inhibitor, Compound 1. The invention also relates to methods of treating a disease, disorder, or syndrome mediated at least in part by modulating in vivo activity of a protein kinase using the pharmaceutical composition and to processes for making the pharmaceutical compositions.

Abstract: A battery material is a core-shell structure, and the core-shell structure includes a core and a shell. The shell surrounds the core. A composition of the core is a silicon material. The shell includes a polymer, the polymer is linear, the polymer includes a first structure and a second structure, the first structure includes a siloxane group, and the second structure includes a carboxyl group or an ester group. The first structure is more adjacent to the core than the second structure.

Abstract: A display device is provided, which includes a first substrate, a first display structure, a second display structure, a first optical film, a second optical film, a first adhesive layer and a second adhesive layer. The first and second display structures are disposed on the first substrate. The first display structure is disposed between the first substrate and the first optical film. The second display structure is disposed between the first substrate and the second optical film. The first and second optical films are separated. The first adhesive layer is disposed between the first display structure and first optical film. The second adhesive layer is disposed between the second display structure and second optical film. The first and second display structures are different from each other and are selected from a liquid-crystal display, an organic light-emitting diode display, an inorganic light-emitting diode display or a laser display.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

Abstract: A contact lens product includes a multifocal contact lens and a buffer solution. The multifocal contact lens is immersed in the buffer solution. The multifocal contact lens includes a central region and at least one annular region. The annular region concentrically surrounds the central region, and a diopter of the annular region is different from a diopter of the central region. The multifocal contact lens is made of silicone hydrogel or hydrogel. The annular region closest to a periphery of the multifocal contact lens is a first annular region.

Abstract: A method for manufacturing an electronic device includes: providing a substrate; forming a plurality of connecting pads and a plurality of conductive portions partially overlapped by the plurality of connecting pads on the substrate; forming a plurality of conductive lines on the substrate, wherein one of the plurality of conductive lines is partially overlapped with one of the plurality of conductive portions, and an insulating layer is disposed between one of the plurality of connecting pads and the one of the plurality of conductive portions; and bonding a plurality of light emitting units to the plurality of connecting pads.

Abstract: A positioning system and a positioning method are provided. The positioning system includes a first positioning device, a second positioning device, a first processing device, and an output device. The first positioning device is used to position a mobile device, and the mobile device contains identification information. The first positioning device generates first positioning information based on the identification information. The second positioning device is used to position an object under test, and the object under test has a feature. The second positioning device generates second positioning information based on the feature. The first processing device generates third positioning information based selectively on the first positioning information and the second positioning information. The output device is used to output the third positioning information.

Abstract: A method for manufacturing a circuit board includes disposing an electronic component in a recess formed in a first circuit substrate, and bonding a second circuit substrate to the first circuit substrate to form a third circuit substrate with the electronic component embedded. The method includes forming an opening in the third circuit substrate to expose the electronic component and an inner surface of the third circuit substrate. The method includes disposing an insulation case in the opening. The insulation case has a first segment directly contacting the electronic component, a second segment facing the inner surface, an inner wall between the first and second segments, a first chamber surrounded by the first segment and the inner wall, and a second chamber surrounded by the second segment and the inner wall. The method includes adding a heat-exchanging fluid into the first chamber.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.

Abstract: A method of manufacturing an electronic device includes the following steps. A substrate is provided, and the substrate has a first surface, a second surface opposite to the first surface and a side surface between the first surface and the second surface. A first circuit is formed on the first surface. The first circuit includes a transistor, a plurality of pads which comprises a first bonding pad, a second bonding pad, a first conductive pad and a first passivation layer. The first passivation layer is disposed on the transistor. The first bonding pad, the second bonding pad and the first conductive pad are respectively disposed on the first passivation layer. A first protection layer is formed on one of the first surface and the second surface. A first cutting lane is formed on the substrate.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: An optimizing method and a computing apparatus for a deep learning network and a computer-readable storage medium are provided. In the method, a value distribution is obtained from a pre-trained model. One or more breaking points in a range of the value distribution are determined. Quantization is performed on a part of values of a parameter type in a first section among multiple sections using a first quantization parameter and the other part of values of the parameter type in a second section among the sections using a second quantization parameter. The value distribution is a statistical distribution of values of the parameter type in the deep learning network. The range is divided into the sections by one or more breaking points. The first quantization parameter is different from the second quantization parameter. Accordingly, accuracy drop can be reduced.