Abstract: A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

Abstract: Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.

Abstract: A memory hank has banks of sense amplifiers positioned in edge memory array mats that are coupled to digit lines with different lengths than banks of sense amplifiers coupled between inner memory array mats. During a main sense phase of a sense operation, a first sense amplifier bank positioned between an edge memory array mat and an inner memory array mat is activated at a first time prior to activation of a second sense amplifier bank positioned in the edge memory array mat at a second time.

Abstract: Provided are a display panel, a display device and a manufacturing method thereof. The display panel includes a display substrate and a color film functional layer located on a light exit side of the display substrate. The display substrate includes a base substrate, a pixel circuit disposed on the base substrate, a light-emitting element layer, and a planarization layer. The light-emitting element layer includes a pixel defining layer, and pixel openings for defining pixel units are formed in the pixel defining layer. The color film functional layer includes a planarization transparent base layer disposed on a surface away from the display substrate, and a plurality of accommodating grooves in different depths are formed in the planarization transparent base layer. Color filter blocks are arranged in the accommodating grooves, and orthographic projections of the color filter blocks on the display substrate cover the pixel openings of the display substrate.

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

Abstract: Some embodiments include an integrated assembly having a CMOS-containing base containing wordline-driver-circuitry. The wordline-driver-circuitry is subdivided amongst horizontally-extending sub-wordline-driver (SWD) units. Memory cells are over the base, and are arranged in vertically-extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Wordlines extend vertically along the rows. Each of the SWD units is associated with at least two of the wordlines and is configured to simultaneously activate the associated wordlines.

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.

Abstract: A memory device can comprise an arrays of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers of memory cells, and a plurality of vertical sense lines coupled to each of the plurality of tiers of memory cells. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line, wherein each of the plurality of multiplexors includes a first portion and a second portion, the first portion is coupled to the array of memory cells and the second portion is formed on a substrate material. The array of memory cells can further comprise a semiconductor under the array (SuA) circuitry comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.

Abstract: A non-contact key tooth profile learning method and system are provided. The non-contact key tooth profile learning method comprises the following steps: acquiring first profile point cloud data of a key by means of a line laser method; and processing the first profile point cloud data so as to obtain first 3D profile information.

Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.

Abstract: Disclosed is a method for recognizing a bitting code of a key. The method comprises: using a back light source and/or a lateral light source to collect an image of a key to be recognized; and recognizing, on the basis of the image, a bitting code of the key to be recognized. Further disclosed are an apparatus for recognizing a bitting code of a key, and a storage medium and an image collection device. The present disclosure can improve the efficiency of recognizing a bitting code of a key and reduce the wear of the key during a recognition process.