Abstract: A non-contact voltage measuring method and a non-contact voltage measuring system are provided. The non-contact voltage measuring method includes the following steps: measuring a voltage signal source to be measured through a capacitive coupling structure to generate a measurement signal; generating an output signal based on the measurement signal through a signal processing circuit; analyzing the output signal through a sampling unit to generate a sampled signal; and outputting the sampled signal to the trained artificial intelligence model, so that the trained artificial intelligence model outputs a recovery signal.

Abstract: The present invention provides compositions comprising optimized ratios of Red clover phytoestrogens as determined by a proprietary physiologically based pharmacokinetic and pharmacodynamic model. The compositions are useful for modulating, preventing or treating postmenopausal or climacteric symptoms, which include but are not limited to bone loss, bone remodeling, hot flushes and vaginal atrophy. The present invention also provides methods for modulating, preventing or treating postmenopausal or climacteric symptoms using the compositions disclosed herein.

Abstract: A method of tuning parameters for image signal processing is provided. The method includes capturing at least one raw image. The method further includes generating a first rendered image by rendering the raw image based on a first parameter value set, and generating a second rendered image by rendering the raw image based on a second parameter value set. The method further includes calculating a first image quality score set for the first rendered image, and calculating a second image quality score set for the second rendered image. The method further includes generating a third parameter value set based on the first parameter value set, the second parameter value set, the first image quality score set, and the second image quality score set.

Abstract: This disclosure is a power supply device including a device body, a fan assembly, an illuminated handle assembly and shock-absorbing fastening elements. The fan assembly is combined in the device body and includes a bracket and a fan, and the bracket includes through holes. The illuminated handle assembly includes a handle, an electrical connecting element, and light-emitting elements. The handle is combined on the bracket and attached to the light-emitting element. The light-emitting element is electrically connected to the electrical connecting element. Each shock-absorbing fastening element is disposed in the fan assembly by each through hole to fix the light-emitting element on a side of the bracket facing the handle. The power supply device controls the light-emitting element through the electrical connecting element. Therefore, the vibration and noise generated during the operation of the fan assembly are reduced, and a power supply device combined with an illuminated handle is provided.

Abstract: A method for tuning a plurality of image signal processor (ISP) parameters of a camera includes performing a first iteration. The first iteration includes extracting image features from an initial image, arranging a tuning order of the plurality of ISP parameters of the camera according to at least the plurality of ISP parameters and the image features, tuning a first set of the ISP parameters according to the tuning order to generate a first tuned set of the ISP parameters, and replacing the first set of the ISP parameters with the first tuned set of the ISP parameters in the plurality of ISP parameters to generate a plurality of updated ISP parameters.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including writing data to an MU of the memory device and performing one or more scan operations on the MU to determine an aggregate value of a data state metric reflective of an amount of erroneous memory cells in the MU. The operations can include determining whether a value of the data state metric reflective of a specified set of erroneous memory cells in the MU satisfies a criterion and identifying a target programming level to which at least one erroneous memory cell was originally programmed. They can also include reprogramming the at least one erroneous memory cell to the target programming level.

Abstract: An electronic device used in the Universal Chiplet Interconnect Express (UCIe) standard is provided. The electronic device includes a substrate and first and second semiconductor devices. The first and second semiconductor devices are disposed on a top surface of the substrate. The substrate includes an interconnect structure electrically connected between the first and second semiconductor devices. The interconnect structure includes a first pad, a first signal trace and first and second via structures. The first pad is located on the top surface of the substrate. The first signal trace is covered by the first and second semiconductor devices. The first via structure is electrically connected between the first pad and the first signal trace. The second via structure is electrically connected between the first via structure and the first signal trace. The first via structure is misaligned with the second via structure.

Abstract: Methods, systems, and devices for techniques for managing a voltage recovery operation are described. In some cases, as part of performing a write command to store data to a set of memory cells, the memory system may store an indication of the initial time at which the write operation occurred, the temperature of the set of memory cells at the initial time, or both. The memory system may subsequently manage an accumulated value based on a duration from the initial time and the temperature of the set of memory cells during the duration. If the accumulated value exceeds an accumulation threshold, the memory system may identify an indication of degradation of the set of memory cells. If the indication exceeds a degradation threshold, the memory system may perform a voltage recovery operation to modify voltages of the set of memory cells.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A galactose rapid quantitative detection system utilizing a test strip containing a concentration of galactose dehydrogenase as the enzyme and a concentration of trehalose as the stabilizer. The system includes a galactose solution composition including a galactose, a buffer and an antioxidant; a test strip, including an enzyme, and a stabilizer; and a meter. The meter includes a power supply unit for providing a signal; a connector for receiving the signal transmitting the signal to the test strip, the signal reacting with the electrochemical information, and the connector transmits the response signal to the meter; a calculation unit for calculating the response signal; an A/D convertor for receiving the response signal from the calculation unit, transforming the response signal into a digital reaction signal; a processor for processing the digital reaction signal; a display for displaying the digital reaction signal; and a digital terminal for receiving the digital reaction signal.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of the memory cell array is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, memory cell conditions related to data retention stress, quick charge loss, back-pattern effects, and/or cross-temperature variations. Based on the determined context, the controller dynamically determines adjustments to wordline and/or other memory cell bias voltages used during the multiplication.

Abstract: Memories might include a controller configured to cause the memory to apply a programming pulse to a memory cell, perform an analog verify phase on the memory cell, in response to the analog verify phase, apply a first voltage level to a corresponding data line of the memory cell that is selected from a group consisting of an inhibit voltage level, a full enable voltage level, and an analog enable voltage level, apply a subsequent programming pulse to the memory cell, perform a digital verify phase on the memory cell, in response to the digital verify phase, apply a second voltage level to the corresponding data line of the memory cell that is selected from a group consisting of the inhibit voltage level and a digital enable voltage level, and apply a next subsequent programming pulse to the memory cell.

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

Abstract: A fruit and vegetable juicer contains: a first holder, a second holder, a filtration mesh, a cutter assembly, and a cap. The second holder includes a drive shaft configured to connect with the cutter assembly so that the cutter assembly rotates at a high speed to cut fruits and vegetables which are fed from an inlet of the cap. The cutter assembly includes a first cutting disc and a second cutting disc. The first cutting disc has a toothed layer surrounding around a peripheral side thereof, a circular orifice defined on a central portion of the first cutting disc, and multiple spaced recesses. The second cutting disc has multiple central teeth, multiple toothed rows radially extending outward from the multiple central teeth, the toothed layer radially extending inward around a peripheral side of the second cutting disc, and the multiple spaced cutouts.

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.

Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.

Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.