Abstract: An apparatus can include a touch-up component. The touch-up component can detect a first charge parameter for a portion of memory of a memory system. The touch-up component can, subsequent to detecting the first charge parameter a particular time interval, detect a second charge parameter for the portion of memory. The touch-up component can determine a charge parameter change per time interval based on the first charge parameter, the second charge parameter, and the particular time interval. The touch-up component can perform a touch-up operation on the portion of memory at a particular time point based on the charge parameter change per time interval.

Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Abstract: A fruit and vegetable juicer contains: a first holder, a second holder, a filtration mesh, a juicing element connected with the filtration mesh and having multiple blades, and a cap. The first holder includes a transmission mechanism configured to drive the juicing element to rotate, the cap includes a feeding inlet configured to feed fruits and vegetables, such that the juicing element rotates to cut and grind fruits and vegetables. The multiple blades of the juicing element have multiple tips extending radially, some of the multiple tips are opposite to the other tips to form multiple forward blades and multiple reverse blades, such that the multiple forward blades and the multiple reverse blades rotate forward or reversely to remove residues and to cut and grind the fruits and vegetables simultaneously.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

Abstract: A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.