Patents by Inventor Yuan Yang

Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335578
    Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 19, 2023
    Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
  • Publication number: 20230337393
    Abstract: An example connector assembly includes a cage, a first liquid cooling tray, a second liquid cooling tray, and a pressuring spring. The cage includes a frame and partitioning walls. The frame and the partitioning walls define an insertion space. The first liquid cooling tray is provided to a top of the cage, with a lower surface of the first liquid cooling tray constituting an upper wall surface of the insertion space. The second liquid cooling tray is provided to a bottom of the cage, with an upper surface of the second liquid cooling tray constituting a lower wall surface of the insertion space. The pressuring spring is positioned within the insertion space.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 19, 2023
    Inventor: Che-Yuan Yang
  • Publication number: 20230335517
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
  • Patent number: 11783029
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency. An example method disclosed herein includes retrieving a log file in a first file format, the log file containing feature occurrence data, generating a first unit operation based on the first file format to extract the feature occurrence data from the log file to a string, the first unit operation associated with a first metadata tag, generating second unit operations to identify respective features from the feature occurrence data, the second unit operations associated with respective second metadata tags, and generating a first sequence of the first metadata tag and the second metadata tags to create a first vector output file of the feature occurrence data.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Chih-Yuan Yang, Yi Gai
  • Patent number: 11784434
    Abstract: A connector assembly is provided and includes a guide shielding cage and a heat sink module. The guide shielding cage has at least one insertion space positioned inside. The heat sink module includes a heat dissipating member, a pressure applying elastic member, a lever member and a supporting elastic member. The heat dissipating member has a thermal coupling portion formed downwardly, the lever member is pivoted to the guide shielding cage, the lever member has a pushed end and a pressure applying end, the supporting elastic member upwardly and elastically supports the heat dissipating member. The heat dissipating member is capable of moving between a releasing position which is higher relative to the insertion space and an acting position which is lower relative to the insertion space and where the thermal coupling portion enters into the insertion space.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 10, 2023
    Assignee: Molex, LLC
    Inventor: Che-Yuan Yang
  • Publication number: 20230317631
    Abstract: Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventors: Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Wen-Chiung Tu, Ying-Yao Lai, Chen-Te Chu, Mao-Nan Wang, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20230317593
    Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Wen-Chiung Tu, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Patent number: 11773262
    Abstract: A resin comprises at least one compound selected from one of the following formulas
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 3, 2023
    Assignee: A.C.R. TECH CO., LTD.
    Inventors: Shih-Hao Liao, Min-Yuan Yang, Ya-Yen Chou, Jheng-Hong Ciou, Cheng-Chung Chen
  • Publication number: 20230298972
    Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Yuan-Yang Hsiao, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11754956
    Abstract: A thickness detection mechanism arranged in a scanner or printer for measuring the thickness of mediums fed through the scanner or printer, which comprising: a conveyor section; at least a idle roller set arranged above the conveyor section, which includes at least a shaft and an idle roller pivotally arranged on the shaft; at least an elastic portion arranged above the shaft; and at least a pressure sensor secured on the elastic portion; wherein the thickness detection mechanism measures the thickness of the medium by measuring the pressure applied on the pressure sensor by the idle roller set as the idle roller set being pushed upward, and thus avoids the medium too thin or too thick to enter the scanner or the printer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: September 12, 2023
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventor: Chih Yuan Yang
  • Publication number: 20230278160
    Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
  • Patent number: 11740450
    Abstract: A structured material is provided that includes a substrate and a porous structured polymer layer disposed thereon. The porous structured polymer layer includes a plurality of voids, and has a high hemispherical reflectance a high a hemispherical thermal emittance. The structured material is thus particularly advantageous for cool-roof coatings, enabling surfaces coated by the material to stay cool, even under strong sunlight. The material can be produced via structuring of polymers in a mixture including a solvent and a non-solvent. Sequential evaporation of the solvent and the non-solvent provide a polymer layer with the plurality of voids.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 29, 2023
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Jyotirmoy Mandal, Yuan Yang, Nanfang Yu
  • Publication number: 20230262929
    Abstract: The present disclosure provides a connector assembly comprising a shielding cage and a liquid cooling cabin. The shielding cage has an insertion space and a window in communication with the insertion space. The liquid cooling cabin is configured to allow a cooling liquid to circulate and flow inside, the liquid cooling cabin comprises a shell having an opening, a thermal coupling cover provided at the opening of the shell, and an elastic sealing unit sealing a gap between the thermal coupling cover and the shell, the thermal coupling cover having a thermal coupling plate entering into the insertion space via the window of the shielding cage, the thermal coupling plate being capable of elastically moving in a direction close to the shell and elastically restoring in a direction away from the shell by a function of the elastic sealing unit.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: You-Qian Lu, Che-Yuan Yang
  • Patent number: 11728295
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
  • Patent number: 11728262
    Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen, Hsiao Ching-Wen, Yao-Chun Chuang
  • Patent number: 11728375
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11729941
    Abstract: A connector assembly includes cages arranged as an upper cage and a lower cage in an up-down direction, a receptacle connector, a first liquid cooling tray and a second liquid cooling tray. Each cage includes a frame and a plurality of partitioning walls provided to the frame, and the frame and the plurality of partitioning walls together define a plurality of insertion space arranged transversely. The first liquid cooling tray is provided to a top portion of the upper cage and constitutes an upper wall surface of each of the plurality of insertion space of the upper cage. The second liquid cooling tray is provided between the upper cage and the lower cage, constitutes a lower wall surface of each of the plurality of insertion spaces of the upper cage, and constitutes an upper wall surface of each of the plurality of insertion space of the lower cage.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 15, 2023
    Assignee: Molex, LLC
    Inventor: Che-Yuan Yang
  • Patent number: 11713202
    Abstract: A foldable baffle structure is mounted to a tray of a scanner or a printer. The foldable baffle structure includes two limiting components mounted to the tray. Each limiting component includes a sliding element, a stopping element, a guiding element and a pivoting element. Middles of the two sliding elements of the two limiting components have two accommodating spaces penetrating through top surfaces and bottom surfaces of the two sliding elements. The two stopping elements of the two limiting components are mounted in the accommodating spaces of the two limiting components. A middle of one end surface of the stopping element protrudes outward to form a pivoting portion. The guiding element is mounted around an outside of the pivoting portion. The pivoting element is pivotally disposed in the stopping element.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 1, 2023
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Yuan Yi Lin, Chih Yuan Yang
  • Patent number: 11715756
    Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
  • Patent number: 11705384
    Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Dian-Hau Chen, Yen-Ming Chen