Patents by Inventor Yue Lin

Yue Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230259020
    Abstract: A lithography system includes an exposure device and a reticle structure disposed in the exposure device. The exposure device includes a reticle having patterned features, a membrane having a boarder section, and a frame disposed and forming an enclosure between the reticle and the membrane to encircle the patterned features. The frame includes a plurality of holes including at least one slit-shaped hole having one side formed by the reticle and three sides formed by the frame.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 17, 2023
    Inventor: Yun-Yue LIN
  • Publication number: 20230251566
    Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue LIN
  • Publication number: 20230251680
    Abstract: A voltage regulation integrated circuit (IC) includes a first transistor, a feedback circuit, a bias circuit, an amplifier circuit, and a transient coupling circuit. The first transistor is configured to generate an output voltage according to an input voltage and a control voltage. The feedback circuit is configured to generate a feedback voltage according to the output voltage. The output voltage includes an AC component. The bias circuit is configured to generate a first bias voltage. The amplifier circuit is configured to generate the control voltage according to the first bias voltage and the feedback voltage. The transient coupling circuit is configured to generate a coupling voltage according to the AC component and to assist the change of the first bias voltage according to the coupling voltage, so that the output voltage is maintained at a voltage level.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 10, 2023
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Jyun WANG, Kai-Yin LIU, Kai-Yue LIN
  • Patent number: 11694425
    Abstract: Aspects of the present disclosure relate to multi-spectrum visual object recognition. A first image corresponding to visible light and a second image corresponding to invisible light with respect to an object can be obtained. A first contour of the object can be identified based on the first image. A second contour of the object can be identified based on the second image. The first contour of the object and the second contour of the object can be integrated to generate a multi-spectrum contour of the object. The object can be recognized using the multi-spectrum contour of the object.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: July 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Yue Lin, Li Cao, Jing Bai, Mu Wei, Bing Qian
  • Patent number: 11662661
    Abstract: A reticle structure includes a reticle having patterned features and a first border section enclosing the patterned features. The reticle structure includes a membrane having a middle section a second border section enclosing the middle section. The reticle structure includes a frame disposed between the membrane and the reticle to mount the membrane over the patterned features of the reticle. The frame creates an enclosure between the reticle and the membrane and encircles the patterned features of the reticle. The frame includes a plurality of holes and the plurality of holes produces a threshold percentage of opening in the frame to maintain an equalized pressure difference between the enclosure and outside the enclosure below a threshold pressure.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11656544
    Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11637558
    Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 25, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Patent number: 11637559
    Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: April 25, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20230071118
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The absorber layer includes one or more layers of an Ir based material, a Pt based material or a Ru based material.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue LIN
  • Publication number: 20230069583
    Abstract: A pellicle for a reflective photo mask includes a frame, a core layer having a front surface and a rear surface, and disposed over the frame, a first capping layer disposed on the front surface of the core layer, an anti-reflection layer disposed on the first capping layer, a barrier layer disposed on the anti-reflection layer, and a heat emissive layer disposed on the barrier layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventor: Yun-Yue LIN
  • Publication number: 20230061320
    Abstract: A pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle. The pellicle frame further includes a bottom surface of the frame defines only a single recess therein. The pellicle frame further includes a gasket configured to fit within the single recess.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 2, 2023
    Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN
  • Publication number: 20230036760
    Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.
    Type: Application
    Filed: July 11, 2022
    Publication date: February 2, 2023
    Inventors: KAI-YUE LIN, HSUAN-TING HO, LIANG-WEI HUANG, CHI-HSI SU
  • Publication number: 20230025101
    Abstract: An analog front-end device includes an amplifier circuit, a first gain control circuit, and a tracking circuit. The amplifier circuit is configured to generate a first output signal according to a first input signal. The first gain control circuit is configured to set a first electronic component according to a first gain control signal and transmit the first input signal to a first input terminal of the amplifier circuit via the first electronic component, in which a terminal of the first electronic component is selectively coupled to the first input terminal or a first predetermined node. The tracking circuit is configured to adjust a level of the first predetermined node according to a level of the first input terminal, in order to reduce a voltage difference between the first input terminal and the first predetermined node.
    Type: Application
    Filed: June 2, 2022
    Publication date: January 26, 2023
    Inventors: JIAN-RU LIN, KAI-YUE LIN, YU-TING CHIU
  • Patent number: 11526073
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Publication number: 20220393694
    Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.
    Type: Application
    Filed: November 3, 2021
    Publication date: December 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20220393693
    Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.
    Type: Application
    Filed: December 14, 2021
    Publication date: December 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Patent number: 11506971
    Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle; and a bottom surface of the frame defines only a single recess therein. The pellicle further includes a gasket configured to fit within the single recess.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chue San Yoo, Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin
  • Patent number: 11500282
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The absorber layer includes one or more layers of an Ir based material, a Pt based material or a Ru based material.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Publication number: 20220358320
    Abstract: Aspects of the present disclosure relate to multi-spectrum visual object recognition. A first image corresponding to visible light and a second image corresponding to invisible light with respect to an object can be obtained. A first contour of the object can be identified based on the first image. A second contour of the object can be identified based on the second image. The first contour of the object and the second contour of the object can be integrated to generate a multi-spectrum contour of the object. The object can be recognized using the multi-spectrum contour of the object.
    Type: Application
    Filed: May 10, 2021
    Publication date: November 10, 2022
    Inventors: Yue Lin, Li Cao, Jing Bai, Mu Wei, Bing Qian
  • Publication number: 20220357649
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process. The apparatus includes a mask defining a circuit pattern to be transferred. The apparatus further includes a pellicle including a pattern formed in a first surface, wherein the pellicle is attached to the mask at the first surface. The apparatus also includes an adhesive material layer disposed between the mask and the first surface. The pattern may include a plurality of capillaries. Each capillary of the plurality of capillaries may have a dimension in a plane of the first surface between about 1 ?m and about 500 ?m. Each capillary of the plurality of capillaries may have a ratio of depth to width greater than or equal to about 100. The adhesive material layer may include an adhesive having a glass transition temperature (Tg) greater than room temperature.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventor: Yun-Yue Lin