Patents by Inventor Yue Lin

Yue Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489867
    Abstract: Systems and methods for classifying and mitigating security threats in a digital communication network are provided. A digital communication that has been identified as suspicious may be parsed to identify various content indicators contained in the communication. Processing may then be performed on the digital communication to determine if the digital communication comprises malicious content. Mitigation activities may be performed when malicious content is identified.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 1, 2022
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Mackenzie Kyle, Dennis Rhodes, Benjamin Arnold, Oscar Chan, Bradley N. Gunner, Rohith Kondeti, Yue Lin
  • Patent number: 11489539
    Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: November 1, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Patent number: 11481451
    Abstract: Systems and methods for ingesting and enhancing data in a distributed processing framework. The system includes at least a data ingestion system configured to access data or datasets from one or more data sources. The data is accessed via the data ingestion system and includes metadata defining a plurality of attributes. The attributes are identified in the metadata, via the data ingestion system, and may be applied to the data or dataset for enhancing the data or dataset. Application of the attributes to the data results in enhancements that may include joining the data, enriching the data, or other enhancements accomplished via manipulation of the data via the data ingestion system.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: October 25, 2022
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Matthew Yazdi, Manish Doshi, Fazil Syed, Smitha Vijayendra, Grant Poladian, Yue Lin
  • Publication number: 20220334463
    Abstract: A mask for extreme ultraviolet (EUV) lithography includes a multilayer (ML) stack including alternating metal and semiconductor layers disposed over a first surface of a mask substrate, a capping layer disposed over the ML stack, and an absorber layer disposed over the capping layer. An image pattern is formed in the absorber layer. A border layer surrounding the image pattern is disposed over the absorber layer.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventor: Yun-Yue LIN
  • Publication number: 20220337259
    Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
    Type: Application
    Filed: February 14, 2022
    Publication date: October 20, 2022
    Inventors: SHIH-HSIUNG HUANG, KAI-YUE LIN, WEI-JYUN WANG, SHENG-YEN SHIH
  • Publication number: 20220329253
    Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 13, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20220326597
    Abstract: A method of forming an extreme ultraviolet (EUV) mask including forming a multilayer stack comprising alternating stacked Mo-containing layer and Si-containing layer over a mask substrate, forming a first nitride layer over the multilayer stack forming a capping layer over the multilayer stack, forming an absorber layer over the capping layer, and etching the absorber layer to form a pattern in the absorber layer.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 13, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yun-Yue LIN
  • Patent number: 11454881
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process. The apparatus includes a mask defining a circuit pattern to be transferred. The apparatus further includes a pellicle including a pattern formed in a first surface, wherein the pellicle is attached to the mask at the first surface. The apparatus also includes an adhesive material layer disposed between the mask and the first surface. The pattern may include a plurality of capillaries. Each capillary of the plurality of capillaries may have a dimension in a plane of the first surface between about 1 ?m and about 500 ?m. Each capillary of the plurality of capillaries may have a ratio of depth to width greater than or equal to about 100. The adhesive material layer may include an adhesive having a glass transition temperature (Tg) greater than room temperature.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Publication number: 20220283493
    Abstract: A first capping layer is deposited over a substrate. A network of nanowires is grown over the first capping layer. A second capping layer is deposited over the network of nanowires. The substrate is etched to form a frame of a pellicle. The first capping layer and the second capping layer are patterned to form a membrane of the pellicle, wherein the patterning reduces a material of the first capping layer and the second capping layer to form a coating on the nanowires.
    Type: Application
    Filed: June 17, 2021
    Publication date: September 8, 2022
    Inventors: YUN-YUE LIN, CHEN-CHIEH YU
  • Publication number: 20220269163
    Abstract: A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventor: Yun-Yue LIN
  • Publication number: 20220252986
    Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue LIN
  • Patent number: 11402745
    Abstract: A mask for extreme ultraviolet (EUV) lithography includes a multilayer (ML) stack including alternating metal and semiconductor layers disposed over a first surface of a mask substrate, a capping layer disposed over the ML stack, and an absorber layer disposed over the capping layer. An image pattern is formed in the absorber layer. A border layer surrounding the image pattern is disposed over the absorber layer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Publication number: 20220229360
    Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: AMO CHEN, YUN-YUE LIN, TA-CHENG LIEN, HSIN-CHANG LEE, CHIH-CHENG LIN, JENG-HORNG CHEN
  • Publication number: 20220197132
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Patent number: 11358124
    Abstract: Disclosed is a preparation method of a nanometer metal oxide supported carrier based on anodic oxidation, comprising: Step 1: adding electrolyte to a reaction pool, and fixing the cathode and the anode oppositely, wherein the cathode is a metal plate that is identical to the nano-metal oxide, and the anode is a carrier metal material; Step 2: stirring the electrolyte at a constant speed, wherein the revolution speed is not lower than 500 rpm; Step 3: switching power on; setting the output voltage between 10 v and 50 v; and subjecting the metal plate of the anode to anodic oxidation reaction, wherein metal oxide nanotubes/nano particles are generated on the surface; under the action of stirring, the metal oxide nanotubes/nano particles on the anode surface are dissolved and shed off into the electrolyte; under the action of the electric field force, the dissolved and shed-off nano fragments migrate towards the cathode and are adhered to the surface of the cathode material, thereby forming a nano-metal oxide fi
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 14, 2022
    Assignee: SHANGHAI MARITIME UNIVERSITY
    Inventors: Qun Qian, Daolun Feng, Yue Lin
  • Patent number: 11360376
    Abstract: A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11356185
    Abstract: A method and a measuring apparatus for measuring noise of a device under test (DUT) is provided, wherein the DUT is connected to a link partner (LP) device via a cable, and the measuring apparatus is coupled to the DUT and LP device. The method includes: controlling the LP device to transmit a far-end data sequence to the DUT according to transmission data; controlling the DUT to recover the transmission data for generating aided-data sequence according to the transmission data, wherein the aided-data sequence is configured to perform cancellation with a received far-end data sequence to generate a cancellation result; generating a first noise value and a second noise value in a first training phase and a second training phase, respectively; and estimating noise from at least one circuit according to the first noise value and the second noise value.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: June 7, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Liang-Wei Huang, Kuei-Ying Lu, Hsuan-Ting Ho
  • Patent number: 11354522
    Abstract: A method and system for obtaining wire information, includes a RFID tag, a RFID reader, and a data center. The RFID tact obtains the sensing information of the wire and transmits the sensing information and identification information of the RFID tag. The RFID reader transmits high-frequency electromagnetic waves to trigger the RFID tact and transmits and receives sensing information and identification information sent by the RFID tag. The data center is communicatively connected with the RFID reader and determines the type of the received sensing information based on the received sensing information and identification information for data analysis.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 7, 2022
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventors: Zhi-Cheng Yu, Xin-Yue Lin
  • Patent number: 11340525
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Patent number: 11314169
    Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin