Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a doped III-V semiconductor layer, a gate, a source electrode, and a drain electrode. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and has opposite first sidewalls which recessed inward toward a body of the doped III-V semiconductor layer between the sidewalls to make a curved profile located at a bottom of the doped III-V semiconductor layer. The gate electrode is disposed above the doped III-V semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is located between the source and drain electrodes.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a doped nitride-based semiconductor layer, a plurality of negatively-charged ions, a source electrode, and a drain electrode. The negatively-charged ions are selected from a highly electronegative group and distributed within a plurality of depletion regions which extend downward from the doped nitride-based semiconductor layer and are located beneath the gate electrode. Any pair of the adjacent depletion regions are separated from each other. The source electrode is disposed above the second nitride-based semiconductor layer and spaced apart from the depletion regions. The drain electrode is disposed above the second nitride-based semiconductor layer and spaced apart from the depletion regions.

Abstract: A nitride-based semiconductor circuit includes a nitride-based semiconductor carrier, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, connectors, a connection line, and a power supply line. The first nitride-based semiconductor layer is disposed over the nitride-based semiconductor carrier. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The connectors are disposed on the second nitride-based semiconductor layer. The connection line electrically connects to one of the connectors. The power supply line electrically to the nitride-based semiconductor carrier. A heterojunction is formed between the first and the second nitride-based semiconductor layers. A potential difference is applied between the power supply line and the connection line.

Abstract: A nitride-based semiconductor device including a first and a second nitride-based semiconductor layers, a source electrode and a drain electrode, and a gate structure. The gate structure includes at least one conductive layer and two or more doped nitride-based semiconductor layers. The at least one conductive layer includes metal, and is in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The two or more doped nitride-based semiconductor layers are in contact with the second nitride-based semiconductor layer and abut against the conductive layer, so as to form contact interfaces abutting against the metal-semiconductor junction with the second nitride-based semiconductor.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.

Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a gate electrode, and a drain structure. The drain structure includes a first doped nitride-based semiconductor layer, an ohmic contact electrode, and a conductive layer. The first doped nitride-based semiconductor layer is in contact with the second nitride-based semiconductor layer to form a first contact interface. The ohmic contact electrode is in contact with the second nitride-based semiconductor layer to form a second contact interface. The conductive layer includes metal and in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The conductive layer is connected to the first doped nitride-based semiconductor layer and the ohmic contact electrode, and the ohmic contact interface is farther away from the gate electrode than the first contact interface and the second contact interface.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. The semiconductor device further includes a dielectric layer disposed on the barrier layer and defining a first recess exposing a portion of the barrier layer. The semiconductor device further includes a first spacer disposed within the first recess, wherein the first spacer comprises a surface laterally connecting the dielectric layer to the barrier layer.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode a first strain-compensating layer, and a first protection layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed between the source and drain electrodes. The first strain-compensating layer is disposed above the second nitride-based semiconductor layer and between the drain and gate electrodes.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a drain electrode, a gate electrode, and a first and a second stress modulation layers. The first nitride-based semiconductor layer has a first thickness. The second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer to form a heterojunction therebetween. The second nitride-based semiconductor layer has a second thickness, and a ratio of the first thickness to the second thickness is in a range from 0.5 to 5. The first and the second stress modulation layers provide a first and a second drift regions of the second nitride-based semiconductor layer with stress, respectively, resulting in induction of a first and a second 2DHG regions within the first and the second drift regions, respectively.

Abstract: A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a channel layer, a barrier layer, a p-type doped III-V layer, a gate, a drain, and a doped semiconductor layer. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. The gate is disposed on the p-type doped III-V layer. The drain is disposed on the barrier layer. The doped semiconductor layer is disposed on the barrier layer and is covered by the drain. The drain has a first portion located between the p-type doped III-V layer and an entirety of the doped semiconductor layer.

Abstract: A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first protection layer, a first spacer, and a gate. The dielectric layer is disposed on the barrier layer. The first protection layer is disposed on the barrier layer, in which the first protection layer extends from a first sidewall of the dielectric layer to a top surface of the barrier layer. The first spacer is disposed on and received by the first protection layer, in which a top end of the first protection layer comprises a first curved surface between the first spacer and the dielectric layer. The gate is disposed on the barrier layer, the dielectric layer, and the first spacer. The gate extends from a top surface of the dielectric layer and at least along the first curved surface of the first protection layer to make contact with the top surface of the barrier layer.

Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.