Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first S/D electrode, and a second S/D electrode. The buffer includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first nitride-based semiconductor layer is disposed over the buffer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The gate electrode and the first and second S/D electrodes are disposed over the second nitride-based semiconductor layer. Profiles of the first and second S/D electrodes are asymmetric with respect to the gate electrode, such that a bottom surface of the first S/D electrode is deeper than that of the second S/D electrode with respect to the gate electrode.

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. A first nitride-based semiconductor layer is disposed over the buffer. A shield layer is disposed between the buffer and the first nitride-based semiconductor layer and includes a first isolation compound that has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, in which the first isolation compound is made of at least one two-dimensional material which includes at least one metal element. A second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The pair of S/D electrodes and the gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.

Abstract: Some embodiments of the present disclosure provide a semiconductor device, including a substrate, a channel layer, a barrier layer, a p-type doped III-V layer, a source, a drain and a doped semiconductor layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. A gate is disposed on the p-type doped III-V layer. The source and the drain are arranged on two opposite sides of the gate. The doped semiconductor layer is provided with a first side close to the gate and a second side away from the gate. The drain covers the first side of the doped semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

Abstract: The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer and a gate structure. The gate structure includes a first portion and a second portion on the first portion. The first portion is on the III-V material layer. The first portion has a first surface and a second surface opposite to the first surface and adjacent to the III-V material layer. A length of the second surface of the first portion of the gate structure is less than a length of the first surface of the first portion of the gate structure. A length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.

Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first protection layer, a first spacer, and a gate. The dielectric layer is disposed on the barrier layer. The first protection layer is disposed on the barrier layer, in which the first protection layer extends from a first sidewall of the dielectric layer to a top surface of the barrier layer. The first spacer is disposed on and received by the first protection layer, in which a top end of the first protection layer comprises a first curved surface between the first spacer and the dielectric layer. The gate is disposed on the barrier layer, the dielectric layer, and the first spacer. The gate extends from a top surface of the dielectric layer and at least along the first curved surface of the first protection layer to make contact with the top surface of the barrier layer.

Abstract: The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics.

Abstract: The present invention relates to a semiconductor device having an improved gate leakage current. The semiconductor device includes: a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, thereby improving the gate leakage current phenomenon.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a barrier layer disposed above the substrate, and a dielectric layer disposed on the barrier layer and defining a first recess. The semiconductor device further includes a spacer disposed within the first recess and a gate disposed between a first portion of the spacer and a second portion of the spacer, wherein the gate defining a first recess.

Abstract: A semiconductor device includes first and second nitride semiconductor layers, a source, a drain, a gate structure, first and second p-type doped nitride semiconductor compound islands. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The source, the drain, and the gate structure are disposed on the second nitride semiconductor layer. The drain viewed in a direction normal to the second nitride semiconductor layer extends longitudinally in an extending direction. The gate structure is between the source and the drain. The first p-type doped nitride semiconductor compound islands are disposed on the second nitride semiconductor layer and arranged adjacent to the drain along the extending direction. The second p-type doped nitride semiconductor compound island is disposed between the gate structure and the second nitride semiconductor layer.

Abstract: An indexing value may be determined, transparently with respect to a data user, based on a desired plaintext item of data and a transformation expression. The indexing value may be used to access an entry in an indexing structure to obtain a corresponding CryptoJSON record which includes a non-deterministically encrypted ciphertext item. Different versions of an export policy may change the ways in which the search is performed based on calculation of a numerical representation of an ECCN for the vendor access. In another embodiment, an indexing structure for a CryptoJSON recordset may be accessed. Positions of items of the indexing structure may be based on corresponding plaintext items. References related to the corresponding plaintext items in the indexing structure may be encrypted and other information in the indexing structure may be unencrypted.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N(III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.