Patents by Inventor Yuichi Takeuchi

Yuichi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220102485
    Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 31, 2022
    Inventors: Hidefumi TAKAYA, Yuichi TAKEUCHI, Yukihiko WATANABE
  • Publication number: 20220045211
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Inventors: Yuichi TAKEUCHI, Yasuhiro EBIHARA, Masahiro SUGIMOTO, Yusuke YAMASHITA
  • Publication number: 20220045172
    Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Inventors: Aiko KAJI, Yuichi TAKEUCHI, Shuhei MITANI, Ryota SUZUKI, Yusuke YAMASHITA
  • Publication number: 20220005928
    Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
    Type: Application
    Filed: September 16, 2021
    Publication date: January 6, 2022
    Inventors: Yuichi TAKEUCHI, Ryota SUZUKI, Tatsuji NAGAOKA, Sachiko AOI
  • Patent number: 11201216
    Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 14, 2021
    Assignee: DENSO CORPORATION
    Inventors: Aiko Kaji, Yuichi Takeuchi, Shuhei Mitani, Ryota Suzuki, Yusuke Yamashita
  • Patent number: 11201239
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 14, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Yasuhiro Ebihara, Masahiro Sugimoto, Yusuke Yamashita
  • Publication number: 20210384343
    Abstract: A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventors: YUICHI TAKEUCHI, KATSUMI SUZUKI, YUSUKE YAMASHITA, TAKEHIRO KATO
  • Patent number: 11177353
    Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 16, 2021
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Ryota Suzuki, Tatsuji Nagaoka, Sachiko Aoi
  • Patent number: 11160442
    Abstract: An endoscope apparatus includes a spectroscopic section disposed on an optical axis of return light from an object irradiated with visible light, first excitation light and second excitation light including a longer wavelength than a wavelength of the first excitation light and configured to separate and emit the light of a second wavelength band other than light of a first wavelength band, a first excitation light cut filter configured to block a wavelength band of one of the first excitation light and the second excitation light included in the return light, and a second excitation light cut filter configured to block a wavelength band of another excitation light of the first excitation light and the second excitation light and a wavelength band of the visible light.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 2, 2021
    Assignee: OLYMPUS CORPORATION
    Inventors: Misa Tsuruta, Toshiaki Watanabe, Yuichi Takeuchi, Hiroki Uchiyama
  • Publication number: 20210324517
    Abstract: A semiconductor manufacturing device includes: a thin film formation portion that includes a chamber; and a supply gas unit that introduces a supply gas into the chamber. The supply gas unit includes: multiple supply pipes; a raw material flow rate controller that is installed on each of the multiple supply pipes, and controls a flow rate; a collective pipe that is connected to the multiple supply pipes, and generates a mixed gas; multiple distribution pipes connected to a downstream side of the collective pipe; a pressure controller that is installed on one distribution pipe, and adjusts a mixed gas pressure; and a distribution flow rate controller that is installed on a distribution pipe different from the distribution pipe provided with the pressure controller, and controls a flow rate of the mixed gas.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Hiroaki FUJIBAYASHI, Yuichi TAKEUCHI
  • Patent number: 11107911
    Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Shuhei Mitani, Yasuhiro Ebihara, Yusuke Yamashita, Tadashi Misumi
  • Patent number: 11049966
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: June 29, 2021
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akira Amano, Takayuki Satomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Publication number: 20210005744
    Abstract: A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Yasuhiro EBIHARA, Yuichi TAKEUCHI, Hidefumi TAKAYA, Yukihiro WATANABE
  • Publication number: 20200381313
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Inventors: Akira AMANO, Takayuki SATOMURA, Yuichi TAKEUCHI, Katsumi SUZUKI, Sachiko AOI
  • Publication number: 20200345614
    Abstract: A bodypainting ink includes a coloring agent, a solvent, and a resin. The coloring agent includes an anion coloring agent, the resin includes a cation monomer, and a molar ratio of cations, constituting the cation monomer, to anions, constituting the anion coloring agent, is 1 or more.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Inventor: Yuichi Takeuchi
  • Patent number: 10790201
    Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: September 29, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akira Amano, Takayuki Satomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10784335
    Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 22, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Shinichiro Miyahara, Atsuya Akiba, Katsumi Suzuki, Yukihiko Watanabe
  • Patent number: 10748780
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 18, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeyuki Takagi, Masaki Shimomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10741715
    Abstract: The present invention addresses the issue of providing: a light-receiving element that has an absorption layer of germanium (Ge), is capable of efficiently receiving near infrared light having a large light-reception sensitivity in the absorption layer, from a free space, and has high productivity and low production cost; and a near infrared light detector comprising said light-receiving element. This light-receiving element 10 has, laminated in order upon a substrate 20, an amplification layer 30 containing silicon (Si), an absorption layer 40 containing germanium (Ge), and an antireflection layer 50. The amplification layer 30 has, in order upon the substrate 20, at least an n-doped n-Si layer 31 and a p-doped p-Si layer 33. The absorption layer 40 has at least a p-doped p-Ge layer 42.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: August 11, 2020
    Assignees: Konica Minolta, Inc., The University of Tokyo
    Inventors: Yuichi Takeuchi, Takuji Hatano, Yasuhiko Ishikawa
  • Patent number: 10734515
    Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 4, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Katsumi Suzuki, Yukihiko Watanabe