Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

Abstract: An adhesive tape is used for fixing a member constituting an electronic apparatus and includes an adhesive layer (A) and a base material (B). The adhesive layer (A) contains an adhesive containing a styrene-based block copolymer and an adhesiveness-imparting resin. The adhesive has a Trouton ratio of 3 or more and 90 or less when the adhesive composition is made into a toluene solution having a solid concentration of 25% (w/w) and is subjected to measurement at 35° C.

Abstract: A semiconductor manufacturing device includes: a thin film formation portion that includes a chamber; and a supply gas unit that introduces a supply gas into the chamber. The supply gas unit includes: multiple supply pipes; a raw material flow rate controller that is installed on each of the multiple supply pipes, and controls a flow rate; a collective pipe that is connected to the multiple supply pipes, and generates a mixed gas; multiple distribution pipes connected to a downstream side of the collective pipe; a pressure controller that is installed on one distribution pipe, and adjusts a mixed gas pressure; and a distribution flow rate controller that is installed on a distribution pipe different from the distribution pipe provided with the pressure controller, and controls a flow rate of the mixed gas.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Abstract: A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: An endoscope apparatus includes a spectroscopic section disposed on an optical axis of return light from an object irradiated with visible light, first excitation light and second excitation light including a longer wavelength than a wavelength of the first excitation light and configured to separate and emit the light of a second wavelength band other than light of a first wavelength band, a first excitation light cut filter configured to block a wavelength band of one of the first excitation light and the second excitation light included in the return light, and a second excitation light cut filter configured to block a wavelength band of another excitation light of the first excitation light and the second excitation light and a wavelength band of the visible light.

Abstract: A semiconductor manufacturing device includes: a thin film formation portion that includes a chamber; and a supply gas unit that introduces a supply gas into the chamber. The supply gas unit includes: multiple supply pipes; a raw material flow rate controller that is installed on each of the multiple supply pipes, and controls a flow rate; a collective pipe that is connected to the multiple supply pipes, and generates a mixed gas; multiple distribution pipes connected to a downstream side of the collective pipe; a pressure controller that is installed on one distribution pipe, and adjusts a mixed gas pressure; and a distribution flow rate controller that is installed on a distribution pipe different from the distribution pipe provided with the pressure controller, and controls a flow rate of the mixed gas.

Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.

Abstract: A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.