Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.

Abstract: A bodypainting ink includes a coloring agent, a solvent, and a resin. The coloring agent includes an anion coloring agent, the resin includes a cation monomer, and a molar ratio of cations, constituting the cation monomer, to anions, constituting the anion coloring agent, is 1 or more.

Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.

Abstract: The present invention addresses the issue of providing: a light-receiving element that has an absorption layer of germanium (Ge), is capable of efficiently receiving near infrared light having a large light-reception sensitivity in the absorption layer, from a free space, and has high productivity and low production cost; and a near infrared light detector comprising said light-receiving element. This light-receiving element 10 has, laminated in order upon a substrate 20, an amplification layer 30 containing silicon (Si), an absorption layer 40 containing germanium (Ge), and an antireflection layer 50. The amplification layer 30 has, in order upon the substrate 20, at least an n-doped n-Si layer 31 and a p-doped p-Si layer 33. The absorption layer 40 has at least a p-doped p-Ge layer 42.

Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.

Abstract: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.

Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.

Abstract: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.

Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

Abstract: A compound semiconductor device includes a semiconductor substrate having a ground layer of a first conductivity type made of a compound semiconductor, a first conductivity type region formed at a corner portion of a bottom of a deep trench formed to the ground layer, and a deep layer of a second conductivity type formed in the deep trench so as to cover the first conductivity type region. A cross section of the first conductivity type region is a triangular shape or a rounded triangular shape in which a portion of the first conductivity type region being in contact with the deep layer is recessed to have a curved surface.

Abstract: A board holding apparatus holds an electric circuit board between a first case and a second case. The board holding apparatus includes locking parts that lock the first case and the second case together in a thickness direction of the electric circuit board such that the first case and the second case are not separated from each other and a bearing surface formed on the second case, the electric circuit board coming into contact with the bearing surface in the thickness direction. The board holding apparatus includes a spring that generates an elastic force, with the locking parts locking the first case and the second case together, the spring being formed on the first case and the elastic force pressing the bearing surface through the electric circuit board.

Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.

Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate that includes a foundation layer; forming a deep trench in the foundation layer; and filling the deep trench with a deep layer having a second conductive type and a limiting layer having the first conductive type. In the filling the deep trench, growth of the deep layer from a bottom of the deep trench toward an opening inlet of the deep trench and growth of the limiting layer from a side face of the deep trench are achieved by: dominant epitaxial growth of a second conductive type layer over a first conductive type layer on the bottom of the deep trench; and dominant epitaxial growth of the first conductive type layer over the second conductive type layer on the side face of the deep trench, based on plane orientation dependency of the compound semiconductor during epitaxial growth.

Abstract: A silicon carbide semiconductor device includes: a main cell region; a sense cell region; a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate having a high impurity concentration layer and a drift layer; an element isolation layer arranged between the main cell region and the sense cell region, and surrounding the sense cell region; and a plurality of electric field relaxation layers arranged between the main cell region and the sense cell region. The MOSFET includes: a base region; a source region; a plurality of deep layers; a trench gate structure; a source electrode; and a drain electrode. The deep layers and the electric field relaxation layers are arranged in a stripe pattern at a predetermined interval.

Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.