Abstract: A liner for an isolation structure is formed in a device layer of a semiconductor device using one or more high dielectric constant (high-k) dielectric materials. The high-k dielectric material(s) of the liner have a dielectric constant that is greater than the dielectric constant of silicon nitride (SixNy), which enables increased passivation to be achieved for the isolation, and enables reduced current leakage to be achieved for integrated circuit structures in the device layer. The isolation structure and/or the liner may be formed by processes that are compatible with subsequent layers and/or structures that are to be formed in the semiconductor device.

Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip, a conductive plug, and a dielectric structure surrounding a portion of the sidewall of the conductive plug. The conductive plug extends from the first semiconductor chip to the second semiconductor chip for electrically connecting the first metallization structure and the second metallization structure. The dielectric structure includes a middle dielectric layer between an outer dielectric layer and an inner dielectric layer. The outer dielectric layer is formed between the first substrate and the middle dielectric layer. The dielectric constant of the outer dielectric layer is greater than the dielectric constant of the middle dielectric layer.

Abstract: A method comprises simulating rays deterministically, monitoring the intensity of the rays as they undergo ray splitting, dynamically switching from deterministic simulation to stochastic simulation when the ray intensity declines to a specified threshold, continuing the stochastic simulation to model interference effects up to the specified threshold, and outputting a simulation result that provides an enhanced representation of light propagation within the waveguide that is based on both the deterministic simulation and the stochastic simulation. Systems and methods are disclosed.

Abstract: A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Abstract: A display device of the subject technology comprises a thin-film-transistor (TFT) layer formed on a substrate and a first layer formed over or under the TFT layer. The TFT layer reflects back unwanted color components of a light produced by a backlight unit (BLU). The display device further includes a second layer to selectively transmit desired colors of the light produced by the BLU to a liquid crystal (LC) layer. The reflected back unwanted color components are recycled to the BLU to reduce a portion of a loss of brightness due to absorption by the second layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1 <RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.

Abstract: Gaze data of a user is received. A display zone corresponding to the gaze data is identified. The display zone is a portion of a display pixel array. The display light generated by the display zone is modulated to shift an optical path of the display light within the display zone.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: A liquid crystal display panel for near-eye display comprises a liquid crystal (LC) panel and a backlight unit (BLU). The BLU includes an array of blue light-emitting diodes (LEDs); a light guide plate configured to guide the blue light from the array of blue LEDs through total internal reflection, and couple portions of the blue light guided by the light guide plate out of the light guide plate; a quantum dot film including quantum dots configured to absorb blue light and emit red and green light; a brightness enhancement film configured to transmit incident light within an angular range and reflect incident light outside of the angular range; and an optical efficiency enhancement film configured to modify an angular beam profile of light from the quantum dot film such that the light transmitted by the brightness enhancement film has a peak intensity in a direction perpendicular to the LC panel.

Abstract: Methods and systems for a liquid crystal display (LCD) device including a backlight with a plurality of light sources (e.g., light emitting diodes (LEDs)) are provided. The LCD device includes an LCD panel and a backlight for illuminating the LCD panel. The backlight includes a plurality of LEDs and a directional light guide plate. The directional light guide plate may be sectioned into quadrants. The plurality of light sources may be stacked and disposed behind the LCD panel positioned relative to directional light guide plate rotation. In an example, the LCD device may include a collimating layer and an extracting layer such that an extraction is variable.

Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate and forming a plurality of first metal lines extending along a first direction in the first semiconductor substrate. Each of the plurality of first metal lines includes a plurality of first discrete portions spaced along the first direction. The method further includes providing a second semiconductor substrate, and forming a second metal line below each of the plurality of first metal lines and extending along the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced along the first direction and the plurality of second discrete portions and the plurality of first discrete portions are alternately staggered along the first direction. The method also includes forming a bonding connector connecting the plurality of second discrete portions to a corresponding first metal line of the plurality of first metal lines.

Abstract: A semiconductor chip includes a first chip feature, and a second chip feature disposed on the first chip feature. The first chip feature includes a first substrate, a first seal ring disposed on the first substrate, a second seal ring disposed on the first substrate, and a first dielectric structure surrounding the first and second seal rings. The second chip feature includes a second substrate, a third seal ring disposed below the second substrate and connected to the first seal ring, a second dielectric structure surrounding the third seal ring, and a conductive ring formed in the second substrate and connected to the third seal ring. The second seal ring, a combination of the first and third seal rings, and a portion of the first dielectric structure and a portion of the second dielectric structure that are disposed between the second seal ring and the combination cooperatively constitute a capacitor.

Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode, a base stack, a magnetic stack, a capping layer and a top electrode stacking along a first direction. The magnetic stack includes two or more free layers separated by one or more spacer layers. Each of the spacer layers is sandwiched by two of the two or more free layers. The spacer layers include a metal oxide, the atoms in which would not diffuse into the free layers during annealing procedure. Therefore, the spacer layers can improve exchange coupling (Aex) and thermal stability in the resulting multilayer magnetic stack.

Abstract: A device structure may be formed by bonding a processor die with at least one memory die using metal-to-metal bonding. The processor die comprises processing units for performing logical operations. The at least one memory die comprises at least two types of memory arrays selected from a static random access memory array, a gain cell random access memory array, and magnetoresistive random access memory array, and a resistive random access memory array. A bonded assembly of the processor die and the at least one memory die is formed. The bonded assembly can be bonded to an interposer using a first array of solder material portions that is bonded to on-die bump structures of the processor die and to a first subset of first bump structures of the interposer.