Abstract: A method includes providing a first electrode, forming a stack of magnetic tunneling junction (MTJ) layers on the first electrode, forming a second electrode on the stack of MTJ layers, and forming a hybrid hard mask on the second electrode. The hybrid hard mask includes a first material layer, a second material layer, and a third material layer. The method also includes patterning the third material layer and the second material layer, patterning the first material layer while using the patterned third material layer and the patterned second material layer as a first mask, patterning the second electrode while using the patterned first material layer as a second mask, and etching the stack of MTJ layers and the first electrode using the patterned second electrode as a third mask. After the etching the stack of MTJ layers and the first electrode, the hybrid hard mask is completely removed.

Abstract: A semiconductor device includes a plurality of interlayer dielectric layers, a memory cell, and a first capping layer. The memory cell is embedded in the interlayer dielectric layers, the first capping layer covers the memory cell and surrounds the sidewalls of the memory cell, the first capping layer includes a hydrogen absorbing material, and the hydrogen absorbing material prevents hydrogen gas from entering the memory cell.

Abstract: A force sensing device is mounted on a tool to sense force, particularly quasi-static and static forces. The force sensing device includes at least one a sensor. A piezoelectric element in the sensor includes a driving portion and a sensing portion. A first voltage is input to the driving portion to generate a vibration in the piezoelectric element and a second voltage in response to the vibration is output from the sensing portion. The second voltage output from the sensing portion is changed as the vibration in the piezoelectric element is suppressed by an external force acting on the force sensing device so variation of the second voltage can be used to measure the external force.

Abstract: A magnetic tunnel junction (MTJ) structure and a memory cell are provided. The MTJ includes a barrier layer, a free layer and a metal oxide cap layer. The free layer is disposed on the barrier layer. The metal oxide cap layer is disposed on the free layer. The metal oxide cap layer has a first surface and a second surface opposite to the first surface. The first surface of the metal oxide cap layer is in contact with the free layer. In a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Abstract: An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Abstract: A party popper contains: a cylinder, a sealing element, a drive element, a flexible fitting element, and a weaken structure. The cylinder includes a first segment and a second segment. The sealing element is a film and is configured to close the second segment. The multiple streamers are filled in the cylinder. A diameter of the drive element is equal to a diameter of the cylinder. The flexible fitting element is made of flexible material with low elastic modulus, and the flexible fitting element includes a cap, a neck section, and a head. The weaken structure surrounds the neck section, and a pulling length is defined to pull off the weaken structure by pulling the weaken structure from the head to the neck section and the cap, such that the weaken structure is pulled off to remove the neck section and the head from the cap.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Abstract: An optical subassembly for switchably focusing or redirecting a light beam may include a polarization element having a polarization-selective beam redirection/focusing property, a first switchable polarization rotator upstream of the polarization element, and a second switchable polarization rotator downstream of the polarization element. A polarizer may be provided immediately downstream of the second switchable polarization rotator. The first and second switchable polarization rotators may be operated in counterphase, so as to mutually offset dependence of angle and wavelength characteristics of the polarization rotators on the switching state of the polarization rotators.

Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.

Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: A medicine image recognition method applied to an electronic device is provided. The method includes obtaining target images by inputting medicine images into a position detection network. Character feature matrices are generated according to the target images and a character recognition network. Image feature matrices are generated by inputting the target images into a category recognition network. Reference matrices are generated according to the image feature matrices and corresponding character feature matrices. Once a matrix to be tested is generated by processing an image to be tested, and a recognition result of the image to be tested is generated according to a similarity between the matrix to be tested and each of the reference matrices.

Abstract: Gaze data of a user is received. A display zone corresponding to the gaze data is identified. The display zone is a portion of a display pixel array. The display light generated by the display zone is modulated to shift an optical path of the display light within the display zone.

Abstract: A liquid crystal pixel includes liquid crystals, a source electrode, and a transparent common electrode layer. The liquid crystals are configured to change an alignment of the liquid crystals in response to a voltage applied across the source electrode and the transparent common electrode layer. The slit in the transparent common electrode layer includes multiple angled sections.

Abstract: A liquid crystal display (LCD) system for a head mounted display includes an LCD panel and a backlight unit. The LCD panel includes a color filter on array (COA) configuration. The backlight unit includes a light adjustment layer to adjust at least one characteristic of illumination light from a light source to tune the illumination light for enlarging an emission cone of display light.

Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.