Abstract: A method of manufacturing a circuit substrate comprising a semiconductor element disposed on a transparent substrate, includes: forming an island-shaped oxide semiconductor layer on the transparent substrate; forming a patterned etch-stop layer made of an insulating material so as to cover at least a center portion of the island-shaped oxide semiconductor layer; depositing a conductive layer over an entire surface of the transparent substrate including a region over the patterned etch-stop layer; forming a patterned resist on the conductive layer; and etching the conductive layer using the patterned resist as a mask to form a patterned conductive layer from the conductive layer, wherein the patterned conductive layer includes a source electrode, a source wiring line, and a drain electrode, and continuing to etch the island-shaped oxide semiconductor thereunder using the patterned conductive layer and the patterned etch-stop layer as a mask to form a cutout in the island-shaped oxide semiconductor layer.

Abstract: This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole.

Abstract: A semiconductor device 1 according to the present invention includes a first electrode G (g1) formed on a substrate B, a first insulation film GI to cover the first electrode g1, a semiconductor film SF including a channel CH, an etching stopper film ES, and a second electrode S (s3). The semiconductor film SF is formed on the first insulation film GI with overlapping the first electrode g1 so that an edge portion SF1 thereof projects outwardly from the first electrode g1 in a plan view. The etching stopper film ES is formed of an insulation film and formed on the semiconductor film SF and the first insulation film GI to cover the channel CH. The etching stopper film ES includes a hole H (hd) in which the edge portion SF1 of the semiconductor film SF is and through which a surface of a portion of the semiconductor film SF near the channel CH is exposed in a plan view.

Abstract: This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole.

Abstract: The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.

Abstract: A liquid crystal panel includes an array substrate, a row control circuit 28, a first trace, a second trace, a gate insulating film, and an organic insulating film. The array substrate11b includes a display area and a non-display area. The row control circuit is arranged in the non-display area. The first trace is a component of the row control circuit. The second trace is a component of the row control circuit and arranged over the first trace so as to cross the first trace. The gate insulating film is arranged between the first trace and the second trace. The organic insulating film includes a hole formed in an area that overlaps at least crossing portions of the first trace and the second trace. The organic insulating film is made of organic resin.

Abstract: A method of manufacturing a circuit substrate comprising a semiconductor element disposed on a transparent substrate, includes: forming an island-shaped oxide semiconductor layer on the transparent substrate; forming a patterned etch-stop layer made of an insulating material so as to cover at least a center portion of the island-shaped oxide semiconductor layer; depositing a conductive layer over an entire surface of the transparent substrate including a region over the patterned etch-stop layer; forming a patterned resist on the conductive layer; and etching the conductive layer using the patterned resist as a mask to form a patterned conductive layer from the conductive layer, wherein the patterned conductive layer includes a source electrode, a source wiring line, and a drain electrode, and continuing to etch the island-shaped oxide semiconductor thereunder using the patterned conductive layer and the patterned etch-stop layer as a mask to form a cutout in the island-shaped oxide semiconductor layer.

Abstract: An array board 11b includes a first diode 29, a contact portion 32, and a static protection portion 51. The first diode 29 includes first electrodes 29a, 29b and a first semiconductor portion 29d. The first electrodes 29a, 29b are formed from a second metal film 38. The first semiconductor portion 29d is connected to the first electrodes 29a, 29b via first diode-side holes 29c1, 29c2. The contact portion 32 includes agate line-side connecting portion 48 and a diode-side connecting portion 50. The gate line-side connecting portion 48 is formed from a first metal film at an end of a gate line 19. The diode-side connecting portion 50 is connected to the gate line-side connecting portion 48 via a contact portion-side hole 49a. The static protection portion 51 includes a static dissipating portion 52 and a static dissipation portion protection portion 53.

Abstract: A semiconductor device includes an oxide semiconductor layer including a first contact region and a second contact region and a channel region located between the first contact region and the second contact region; a source electrode provided on the oxide semiconductor layer so as to be in contact with the first contact region; and a drain electrode provided on the oxide semiconductor layer so as to be in contact with the second contact region. All side faces of the oxide semiconductor layer are located over the gate electrode; a width of the source electrode is greater than a width of the oxide semiconductor layer; and a width of the drain electrode is greater than a width of the oxide semiconductor layer.

Abstract: A semiconductor device (100) according to the present invention includes a thin film transistor (10) having a gate electrode (62a), a first insulating layer (64), an oxide semiconductor layer (66a), a protection layer (68), a source electrode (72as), and a second insulating layer (74). A first connecting portion (30) includes a lower metal layer (72c), an upper metal layer (72c), and an insulating layer (74). A second connecting portion (40) includes a lower metal layer (72d) and an upper conductive layer (17d). A region in which the lower metal layer (72d) is in contact with the upper conductive layer (17d), and a region in which an insulating layer (74) made of a same material as the first insulating layer and a semiconductor layer (66d) made of a same material as the oxide semiconductor layer (66a) are stacked in between the lower metal layer (72d) and the upper conductive layer (17d), are formed in the second connecting portion (40).

Abstract: The present invention prevents electric corrosion even when metal lines that may cause problems when in direct contact with ITO are used as source/drain lines, without increasing the number of steps for manufacturing a TFT substrate. A semiconductor apparatus includes TFTs that each include: a gate electrode included in a gate layer 11a provided on a substrate 20; a semiconductor element 15 provided above the gate layer 11a with a gate insulating film 21 positioned in between; and a source electrode and a drain electrode included in a source layer 12a located across the semiconductor element 15.

Abstract: A semiconductor device (100) according to the present invention includes a thin film transistor (10) having a gate electrode (62a), a first insulating layer (64), an oxide semiconductor layer (66a), a protection layer (68), a source electrode (72as), and a second insulating layer (74). A first connecting portion (30) includes a lower metal layer (72c), an upper metal layer (72c), and an insulating layer (74). A second connecting portion (40) includes a lower metal layer (72d) and an upper conductive layer (17d). A region in which the lower metal layer (72d) is in contact with the upper conductive layer (17d), and a region in which an insulating layer (74) made of a same material as the first insulating layer and a semiconductor layer (66d) made of a same material as the oxide semiconductor layer (66a) are stacked in between the lower metal layer (72d) and the upper conductive layer (17d), are formed in the second connecting portion (40).

Abstract: A liquid crystal panel 11 includes a display area TFT 17, a non-display area TFT 29, and a first interlayer insulator 39. The display area TFT 17 is disposed in a display area AA of an array board 11b. The non-display area TFT 29 is disposed in a non-display area NAA. The non-display area TFT 29 includes a second gate electrode 29a, a second channel 29d, a second source electrode 29b, and a second drain electrode 29c. The second channel 29d is formed from an oxide semiconductor film 36. The second source electrode 29b is connected to the second channel 29d. The second drain electrode 29c is connected to the second channel 29d. The first interlayer insulator 39 is layered at least on the second source electrode 29b and the second drain electrode 29c. The first interlayer insulator 39 has a multilayer structure including a lower first interlayer insulator 39a and an upper first interlayer insulator 39b.

Abstract: A semiconductor device 1 according to the present invention includes a first electrode G (g1) formed on a substrate B, a first insulation film GI to cover the first electrode g1, a semiconductor film SF including a channel CH, an etching stopper film ES, and a second electrode S (s3). The semiconductor film SF is formed on the first insulation film GI with overlapping the first electrode g1 so that an edge portion SF1 thereof projects outwardly from the first electrode g1 in a plan view. The etching stopper film ES is formed of an insulation film and formed on the semiconductor film SF and the first insulation film GI to cover the channel CH. The etching stopper film ES includes a hole H (hd) in which the edge portion SF1 of the semiconductor film SF is and through which a surface of a portion of the semiconductor film SF near the channel CH is exposed in a plan view. The second electrode S (s3) is disposed on the semiconductor film.

Abstract: The array board 11b includes a first diode 29, a common line 25, a first shorting line 31, and the static protection portion 51. The first diode 29 include at least the first semiconductor portion 29d having outer edges 29d1 that cross the outer edges 29a1, 29b1 of first electrodes 29a, 29b in a plan view. The common line 25 is formed from the first metal film 34. The first shorting line 31 is formed from the second metal film 38 and crosses the common line 25. The static protection portion 51 is formed from the second metal film 38 or the protection film 37. At least a portion of the static protection portion 51 overlaps the common line 25 in a plan view. The static protection portion 51 is arranged closer to the first diode 29 than an intersection CPT of the common line 25 and the first shorting line 31. The static protection portion 51 includes at least a static dissipating portion 52 for dissipating static.

Abstract: An array board 11b includes a first diode 29, a contact portion 32, and a static protection portion 51. The first diode 29 includes first electrodes 29a, 29b and a first semiconductor portion 29d. The first electrodes 29a, 29b are formed from a second metal film 38. The first semiconductor portion 29d is connected to the first electrodes 29a, 29b via first diode-side holes 29c1, 29c2. The contact portion 32 includes agate line-side connecting portion 48 and a diode-side connecting portion 50. The gate line-side connecting portion 48 is formed from a first metal film at an end of a gate line 19. The diode-side connecting portion 50 is connected to the gate line-side connecting portion 48 via a contact portion-side hole 49a. The static protection portion includes a static dissipating portion 52 and a static dissipation portion protection portion 53.

Abstract: The present invention provides a circuit substrate that can reduce Cgd capacitance, sufficiently prevent the influence of Cgd capacitance on applied voltage, together with sufficiently make the reliability of the circuit substrate favorable, to provide a method of manufacturing thereof, and a display device.

Abstract: The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.

Abstract: A semiconductor device (100) according to the present invention includes a thin film transistor (10) having a gate electrode (62a), a first insulating layer (64), an oxide semiconductor layer (66a), a protection layer (68), a source electrode (72as), and a second insulating layer (74). A first connecting portion (30) includes a lower metal layer (72c), an upper metal layer (72c), and an insulating layer (74). A second connecting portion (40) includes a lower metal layer (72d) and an upper conductive layer (17d). A region in which the lower metal layer (72d) is in contact with the upper conductive layer (17d), and a region in which an insulating layer (74) made of a same material as the first insulating layer and a semiconductor layer (66d) made of a same material as the oxide semiconductor layer (66a) are stacked in between the lower metal layer (72d) and the upper conductive layer (17d), are formed in the second connecting portion (40).

Abstract: This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole.