Patents by Inventor Yukinobu Nakata
Yukinobu Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9030619Abstract: A semiconductor device (100A) according to the present invention includes: a thin-film transistor (10); a first insulating layer (9) which has been formed over the thin-film transistor (10); a second insulating layer (11) which has been formed on the first insulating layer (9) and which has a hole (21a); and an opaque layer (12a) which is arranged so as to overlap an oxide semiconductor layer (5) when viewed along a normal to the substrate (1). The opaque layer (12a) has been formed in the hole (21a). The opaque layer (12a) has a raised and curved upper surface and the upper surface of the second insulating layer (11) is located closer to the substrate (1) than the upper surface of the opaque layer (12a) is.Type: GrantFiled: November 29, 2011Date of Patent: May 12, 2015Assignee: Sharp Kabushiki KaishaInventors: Atsuhito Murai, Yukinobu Nakata, Shingo Kawashima, Jun Nishimura
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Publication number: 20140347590Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).Type: ApplicationFiled: January 8, 2013Publication date: November 27, 2014Inventors: Tetsuo Fujita, Yoshihito Hara, Yukinobu Nakata
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Publication number: 20140340607Abstract: This semiconductor device (100A) includes: a thin-film transistor (101); a gate line layer; an interlevel insulating layer (14) including a first insulating layer (12) which contacts at least with the surface of a drain electrode (11d); a first transparent conductive layer (15) on the interlevel insulating layer (14); a drain connected transparent conductive layer (15a) arranged on the interlevel insulating layer (14) and not electrically connected to the first transparent conductive layer (15); a dielectric layer (17) arranged on the first transparent conductive layer (15); and a second transparent conductive layer (19a) which is arranged over the dielectric layer (17) so as to overlap at least partially with the first transparent conductive layer (15) with the dielectric layer (17) interposed between them.Type: ApplicationFiled: November 15, 2012Publication date: November 20, 2014Inventors: Yukinobu Nakata, Tetsuo Fujita, Yoshihito Hara
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Patent number: 8860920Abstract: A method of producing a liquid crystal display device according to the present invention includes: a step of providing a liquid crystal panel (110); a step of, through light irradiation while applying a voltage to a mixture via a check terminal (174) and a check line (172) on a rear substrate (130), forming from the mixture a liquid crystal layer (140) containing a liquid crystal compound and an alignment sustaining layer (150, 160) resulting through polymerization of a photopolymerizable compound; and a step of, after forming the liquid crystal layer (140) and the alignment sustaining layer (150, 160), applying a voltage across the liquid crystal layer (140) from the check terminal (172) to check the liquid crystal panel (110).Type: GrantFiled: July 23, 2010Date of Patent: October 14, 2014Assignee: Sharp Kabushiki KaishaInventors: Shogo Nishiwaki, Kunihiro Tashiro, Yukinobu Nakata, Takayuki Hayano
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Patent number: 8829517Abstract: A TFT substrate (20a) includes: an insulating substrate (10a); a plurality of source terminals (15) located on the insulating substrate (10a); and a first terminal cover (24) covering part of each of the source terminals (15) and made of an oxide semiconductor. The first terminal cover (24) is removed in a region R between adjacent ones of the source terminals (15).Type: GrantFiled: July 14, 2011Date of Patent: September 9, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Patent number: 8778730Abstract: The present invention provides a highly reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings. The circuit board of the present invention includes an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.Type: GrantFiled: October 25, 2010Date of Patent: July 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Patent number: 8753921Abstract: A method for producing a semiconductor device according to the present invention includes a step of sputtering a target (100A). The target (100A) includes a plurality of target tiles (11A) located while having a gap therebetween; a backing plate (15A) for supporting the plurality of target tiles (11A); and a bonding member (17A) provided between the backing plate (15A) and the plurality of target tiles (11A). The plurality of target tiles (11A) each contain In, Ga and Zn. When the target (100A) is seen in a direction normal thereto from the side on which the plurality of target tiles (11A) are located, the plurality of target tiles (11A) are each smaller than an insulating substrate (1), and the bonding member (17A) cannot be seen through the gap.Type: GrantFiled: September 9, 2011Date of Patent: June 17, 2014Assignee: Sharp Kabushiki KaishaInventors: Tetsuo Fujita, Yukinobu Nakata, Tohru Daitoh
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Patent number: 8692756Abstract: The present invention provides a liquid crystal display device and a method for manufacturing the same that can improve aperture ratio of pixels while securing necessary storage capacitance using a simple configuration even if there is progress in high resolution of pixels. The liquid crystal display device according to the present invention is provided with a plurality of pixels. A thin film transistor array substrate includes gate lines and source lines arranged in a grid pattern on a principal surface of a supporting substrate, transparent pixel electrodes, and thin film transistors. Also, the thin film transistor array substrate includes a gate insulator, a passivation layer, a transparent conductive film, a first insulation layer, and transparent pixel electrodes stacked in order from a supporting substrate side. The transparent pixel electrodes are electrically connected with drain electrodes of the thin film transistors through contact holes formed in the first insulation layer.Type: GrantFiled: April 28, 2010Date of Patent: April 8, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20140027769Abstract: A semiconductor device (100) according to the present invention includes a diode element (10). The diode element (10) includes: a first electrode (3) made of the same electrically conductive film as a gate electrode of a thin film transistor; an oxide semiconductor layer (5); and a second electrode (6) and a third electrode (7) being made of the same electrically conductive film as a source electrode of the thin film transistor and being in contact with the oxide semiconductor layer (5). The oxide semiconductor layer (5) includes offset regions (19) respectively between the first electrode (3) and the second electrode (6) and between the first electrode (3) and the third electrode (7).Type: ApplicationFiled: April 2, 2012Publication date: January 30, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Yukinobu Nakata
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Patent number: 8633481Abstract: A semiconductor device (1000) includes a thin film transistor having a gate line (3a), source and drain lines (13as, 13ad), and an island-like oxide semiconductor layer (7), and a capacitor element (105) having a first electrode (3b) formed from the same conductive film as the gate line (3s), a second electrode (13b) formed from the same conductive film as the source line (13as), and a dielectric layer positioned between the first electrode and the second electrode. A gate insulating film (5) has a layered structure including a first insulating layer (5A) containing an oxide and a second insulating layer (5B) disposed on the side closer to the gate electrode closer than the first insulating film and having a higher dielectric constant than the first insulating film, the layered structure being in contact with the oxide semiconductor layer (7). The dielectric layer includes the second insulating film (5B) but does not include the first insulating film (5A).Type: GrantFiled: August 26, 2011Date of Patent: January 21, 2014Assignee: Sharp Kabushiki KaishaInventors: Jun Nishimura, Yukinobu Nakata, Yoshihito Hara
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Patent number: 8633044Abstract: In a display region of an active matrix substrate, an interlayer insulating film made of a photosensitive organic insulating film, an insulating film different from the interlayer insulating film, and a plurality of pixel electrodes formed on a surface of the interlayer insulating film are provided. In a non-display region of the active matrix substrate, a lead line extended from the display region is formed. In a formation region for a sealing member, the interlayer insulating film is removed, the insulating film is provided to cover part of the lead line, and the sealing member is formed directly on a surface of the insulating film.Type: GrantFiled: January 25, 2012Date of Patent: January 21, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20140014951Abstract: A semiconductor device (100A) according to the present invention includes: an oxide semiconductor layer (4) having a first contact region (4a) and a second contact region (4b) and a channel region (4c) located between the first contact region (4a) and the second contact region (4b); a source electrode (5) formed on the oxide semiconductor layer (4) so as to be in contact with the first contact region (4a); and a drain electrode (6) formed on the oxide semiconductor layer (4) so as to be in contact with the second contact region (4b). All side faces of the oxide semiconductor layer (4) are located over the gate electrode (2); a width of the source electrode (5) is greater than a width of the oxide semiconductor layer (4); and a width of the drain electrode (6) is greater than a width of the oxide semiconductor layer (4).Type: ApplicationFiled: January 5, 2012Publication date: January 16, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Shingo Kawashima, Yukinobu Nakata, Atsuhito Murai, Shinya Tanaka
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Patent number: 8629948Abstract: A liquid crystal display panel includes: a plurality of switching elements each provided on a transparent substrate (10) for each sub-pixel and having a drain electrode (14b); an interlayer insulating film (17) provided to cover the switching elements and including an inorganic insulating film (15) and an organic insulating film (16) sequentially layered; a capacitor electrode (18a) provided on the interlayer insulating film (17); a capacitor insulating film (19) provided to cover the capacitor electrode (18a); a plurality of pixel electrodes (20a) which are provided on the capacitor insulating film (19) and face the capacitor electrode (18a); and a connection region (R) at which the drain electrode (14b) and the capacitor electrode (18a) overlap each other via the inorganic insulating film (15) exposed from the organic insulating film (16).Type: GrantFiled: January 24, 2012Date of Patent: January 14, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20140009713Abstract: A semiconductor device (100A) according to the present invention includes: a thin-film transistor (10); a first insulating layer (9) which has been formed over the thin-film transistor (10); a second insulating layer (11) which has been formed on the first insulating layer (9) and which has a hole (21a); and an opaque layer (12a) which is arranged so as to overlap an oxide semiconductor layer (5) when viewed along a normal to the substrate (1). The opaque layer (12a) has been formed in the hole (21a). The opaque layer (12a) has a raised and curved upper surface and the upper surface of the second insulating layer (11) is located closer to the substrate (1) than the upper surface of the opaque layer (12a) is.Type: ApplicationFiled: November 29, 2011Publication date: January 9, 2014Applicant: Sharp Kabushiki KaishaInventors: Atsuhito Murai, Yukinobu Nakata, Shingo Kawashima, Jun Nishimura
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Publication number: 20130302929Abstract: In a display region of an active matrix substrate, an interlayer insulating film made of a photosensitive organic insulating film, an insulating film different from the interlayer insulating film, and a plurality of pixel electrodes formed on a surface of the interlayer insulating film are provided. In a non-display region of the active matrix substrate, a lead line extended from the display region is formed. In a formation region for a sealing member, the interlayer insulating film is removed, the insulating film is provided to cover part of the lead line, and the sealing member is formed directly on a surface of the insulating film.Type: ApplicationFiled: January 25, 2012Publication date: November 14, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20130270548Abstract: A TFT substrate (20a) includes: an insulating substrate (10a); a plurality of source terminals (15) located on the insulating substrate (10a); and a first terminal cover (24) covering part of each of the source terminals (15) and made of an oxide semiconductor. The first terminal cover (24) is removed in a region R between adjacent ones of the source terminals (15).Type: ApplicationFiled: July 14, 2011Publication date: October 17, 2013Applicant: Sharp Kabushiki KaishaInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20130235292Abstract: A liquid crystal display panel includes: a plurality of switching elements each provided on a transparent substrate (10) for each sub-pixel and having a drain electrode (14b); an interlayer insulating film (17) provided to cover the switching elements and including an inorganic insulating film (15) and an organic insulating film (16) sequentially layered; a capacitor electrode (18a) provided on the interlayer insulating film (17); a capacitor insulating film (19) provided to cover the capacitor electrode (18a); a plurality of pixel electrodes (20a) which are provided on the capacitor insulating film (19) and face the capacitor electrode (18a); and a connection region (R) at which the drain electrode (14b) and the capacitor electrode (18a) overlap each other via the inorganic insulating film (15) exposed from the organic insulating film (16).Type: ApplicationFiled: January 24, 2012Publication date: September 12, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20130181217Abstract: A semiconductor device (100) according to the present invention includes a thin film transistor (10) having a gate electrode (62a), a first insulating layer (64), an oxide semiconductor layer (66a), a protection layer (68), a source electrode (72as), and a second insulating layer (74). A first connecting portion (30) includes a lower metal layer (72c), an upper metal layer (72c), and an insulating layer (74). A second connecting portion (40) includes a lower metal layer (72d) and an upper conductive layer (17d). A region in which the lower metal layer (72d) is in contact with the upper conductive layer (17d), and a region in which an insulating layer (74) made of a same material as the first insulating layer and a semiconductor layer (66d) made of a same material as the oxide semiconductor layer (66a) are stacked in between the lower metal layer (72d) and the upper conductive layer (17d), are formed in the second connecting portion (40).Type: ApplicationFiled: September 30, 2011Publication date: July 18, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Yukinobu Nakata
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Publication number: 20130171771Abstract: A method for producing a semiconductor device according to the present invention includes a step of sputtering a target (100A). The target (100A) includes a plurality of target tiles (11A) located while having a gap therebetween; a backing plate (15A) for supporting the plurality of target tiles (11A); and a bonding member (17A) provided between the backing plate (15A) and the plurality of target tiles (11A). The plurality of target tiles (11A) each contain In, Ga and Zn. When the target (100A) is seen in a direction normal thereto from the side on which the plurality of target tiles (11A) are located, the plurality of target tiles (11A) are each smaller than an insulating substrate (1), and the bonding member (17A) cannot be seen through the gap.Type: ApplicationFiled: September 9, 2011Publication date: July 4, 2013Applicant: Sharp Kabushiki KaishaInventors: Tetsuo Fujita, Yukinobu Nakata, Tohru Daitoh
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Publication number: 20130153904Abstract: A semiconductor device (1000) includes a thin film transistor having a gate line (3a), source and drain lines (13as, 13ad), and an island-like oxide semiconductor layer (7), and a capacitor element (105) having a first electrode (3b) formed from the same conductive film as the gate line (3s), a second electrode (13b) formed from the same conductive film as the source line (13as), and a dielectric layer positioned between the first electrode and the second electrode. A gate insulating film (5) has a layered structure including a first insulating layer (5A) containing an oxide and a second insulating layer (5B) disposed on the side closer to the gate electrode closer than the first insulating film and having a higher dielectric constant than the first insulating film, the layered structure being in contact with the oxide semiconductor layer (7). The dielectric layer includes the second insulating film (5B) but does not include the first insulating film (5A).Type: ApplicationFiled: August 26, 2011Publication date: June 20, 2013Inventors: Jun Nishimura, Yukinobu Nakata, Yoshihito Hara