Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.

Abstract: The present disclosure provides a circuit and a method thereof for setting an SDRAM. The circuit includes at least one register and a controller circuit. The controller circuit is configured to: control the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is utilized for initialing the SDRAM; set value of the at least one register under the initialization setting mode; and set the SDRAM according to the value of the at least one register.

Abstract: A foam and a foaming composition are provided. The foam includes a composite material and a plurality of foam cells, wherein the foam cells are disposed in the composite material. The composite material includes a modified sulfur-containing polymer and a fluorine-containing polymer fiber, wherein a degree of orientation as defined by the ratio I110/I200 is from 1.0 to 1.3, wherein I110 is the X-ray diffraction peak intensity of (110) planes of the modified sulfur-containing polymer and I200 is the X-ray diffraction peak intensity of (200) planes of the modified sulfur-containing polymer.

Abstract: An illumination module is provided. The illumination module includes a light-emitting unit. The light-emitting unit includes a light-emitting element array and a focusing lens array. The light-emitting element array includes a plurality of light-emitting elements. The light-emitting elements are used for generating a plurality of light beams. The focusing lens array includes a plurality of focusing lenses. Each of the light-emitting elements corresponds to at least one of the focusing lenses.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming first channel structures, second channel structures, and third channel structures. The method also includes forming gate dielectric layers surrounding the first channel structures, the second channel structures, and the third channel structures and forming dipole layers over the gate dielectric layers. The method also includes forming a dummy material in a first space between the first and the second channel structures and in a second space between the second and the third channel structures and removing first portions of the dummy material. The method also includes implanting first dopants in the dummy material in the first space and removing second portions of the dummy material in the first space and the second space. The method also includes removing the dipole layers in the top device region and completely removing the dummy material.

Abstract: A blockchain-based method for saving research data is implemented by a processing system. The processing system is connected to a blockchain system, and stores a user account associated with the blockchain system. The method includes sending a deployment request that includes the user account and an application to the blockchain system, in order for the blockchain system to deploy the application associated with the user account on the blockchain system. The method further includes generating and sending a processing request that includes a to-be-processed dataset to the blockchain system, in order for the blockchain system to analyze the to-be-processed dataset using the application so as to obtain a target dataset that corresponds to the to-be-processed dataset and that indicates an analysis result of the to-be-processed dataset, to store the to-be-processed dataset and the target dataset in the blockchain system, and to send the target dataset to the processing system.

Abstract: A memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorption layer. The hydrogen absorption layer absorbs hydrogen, which prevents or reduces the likelihood of the hydrogen diffusing into an underlying metal-oxide channel of the transistor structure. In this way, the hydrogen absorption layer minimizes and/or reduces the likelihood of hydrogen contamination in the metal-oxide channel, which may enable a low current leakage to be achieved for the memory cell structure and reduces the likelihood of data corruption and/or failure of the memory cell structure, among other examples.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A video processing apparatus includes a video encoding circuit and a post-processing circuit. The video encoding circuit receives a first source data, and encodes the first source data to generate a first bitstream, wherein the first source data includes a first source luminance channel data and a first source chrominance channel data, and the first bitstream includes a first compressed luminance channel data and a first compressed chrominance channel data. The post-processing circuit derives an auxiliary compressed chrominance channel data from an auxiliary input, and generates and outputs an output bitstream that includes the first compressed luminance channel data and the auxiliary compressed chrominance channel data.

Abstract: An illumination module is provided. The illumination module includes a light-emitting unit. The light-emitting unit includes a light-emitting element array and a focusing lens array. The light-emitting element array includes a plurality of light-emitting elements. The light-emitting elements are used for generating a plurality of light beams. The focusing lens array includes a plurality of focusing lenses. Each of the light-emitting elements corresponds to at least one of the focusing lenses.

Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.

Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The method also includes forming a dummy gate structure across the fin structure. The method also includes depositing a spacer layer over the fin structure and the dummy gate structure. The method also includes implanting dopants into the spacer layer to form a first doped region vertically overlapping the dummy gate structure and a second doped region over the fin structure without vertically overlapping the dummy gate structure. A middle region of the spacer layer connects the first doped region and the second doped region. The method also includes removing the first doped region and the second doped region of the spacer layer. The method also includes forming a source/drain structure attached to the fin structure after removing the first doped region and the second doped region of the spacer layer.

Abstract: A context-based adaptive binary arithmetic coding (CABAC) decoder includes a bin decode circuit and a context update circuit. The bin decode circuit supports decoding of multiple bins in one cycle. The multiple bins include a first bin and a second bin. The bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts, and updates the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.