Patents by Inventor Yun Cheng

Yun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213314
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung TSAI, Chih-Hsin KO, Clement Hsing Jen WANN, Ya-Yun CHENG
  • Publication number: 20240182904
    Abstract: Provided herein are oligonucleotides (e.g., siRNA) targeting S6K1. Also provided are methods of treating a disease associated with S6K1 expression.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 6, 2024
    Inventors: Claudio Punzo, Anastasia Khvorova, Dimas Echeverria Moreno, Annabelle Biscans, Julia F. Alterman, Matthew Hassler, Shun-Yun Cheng, Jillian Caiazzi
  • Publication number: 20240186305
    Abstract: A device substrate, including a circuit substrate, a first side wiring, a sealant structure, and a second side wiring, is provided. The first side wiring extends from a first surface of the circuit substrate to a second surface of the circuit substrate along a side surface of the circuit substrate. The sealant structure is located above the first surface and covers the first side wiring on the first surface. The second side wiring extends from the sealant structure to the first side wiring located on the side surface and the second surface of the circuit substrate.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 6, 2024
    Applicant: AUO Corporation
    Inventors: Yun Cheng, Hsi-Hung Chen, Hao-An Chuang
  • Publication number: 20240173420
    Abstract: Provided herein are conjugated oligonucleotides that are characterized by efficient and specific eye distribution.
    Type: Application
    Filed: September 29, 2023
    Publication date: May 30, 2024
    Inventors: Claudio Punzo, Anastasia Khvorova, Dimas Echeverria Moreno, Annabelle Biscans, Julia F. Alterman, Matthew Hassler, Shun-Yun Cheng
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Patent number: 11963300
    Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
  • Publication number: 20240113234
    Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 4, 2024
    Inventors: Ya-Yun Cheng, Wen-Ling Lu, Yu-Chien Chiu, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11949920
    Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.
    Type: Grant
    Filed: July 24, 2022
    Date of Patent: April 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Ming-Hsien Lai, Min-Hao Chiu, Chia-Yun Cheng
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 11926901
    Abstract: A method for fabricating nonenzymatic glucose sensor, which comprises steps of: (a) providing a bottom substrate; (b) preparing a graphene layer on the bottom substrate; (c) depositing plural amount of zinc oxide (ZnO) seed crystals on the graphene layer; (d) growing the ZnO seed crystals into columnar nanorods with hydrothermal method; (e) coating a thin film of cuprous oxide (Cu2O) on the surface of the ZnO nanorods by electrochemistry-based electrodeposition; and (f) grafting single-walled carbon nanotubes (SWCNTs) on surface of the Cu2O thin film, by using Nafion fixative composited with SWCNTs. The structure of the above sensor, therefore, comprises a bottom substrate and other components orderly assembled on it, including, from inside to outside, a graphene layer, plural amount of ZnO nanorods, a Cu2O thin film, plural amount of SWCNTs, and the Nafion fixative. Accordingly, the sensor has advantages of low cost, rapid response, and easy for preservation.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 12, 2024
    Assignee: NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Hsi-Chao Chen, Wei-Rong Su, Yun-Cheng Yeh, Chun-Hao Chang
  • Patent number: 11916107
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Chih-Hsin Ko, Clement Hsing Jen Wann, Ya-Yun Cheng
  • Patent number: 11908749
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20240032274
    Abstract: A memory device includes a semiconductor substrate. The memory device includes a stack of channel layers over the semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with the stack of channel layers. The memory device includes a source feature and a drain feature on both sides of the stack of channel layers.
    Type: Application
    Filed: January 30, 2023
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Chun Liou, Chia-En Huang, Ya-Yun Cheng, Chung-Wei Wu
  • Publication number: 20240023338
    Abstract: A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Chun Liou, Zhiqiang Wu, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin
  • Patent number: 11874537
    Abstract: The present invention relates to a display device, comprising: a first substrate comprising a first inner surface, a first outer surface opposite to the first inner surface, a display region, a bonding region adjacent to the display region, a plurality of thin film transistors disposed on the first inner surface and corresponding to the display region; a second substrate opposite to the display region and comprising a second inner surface, a second outer surface opposite to the second inner surface, a first color resist and a second color resist each disposed on the second inner surface; a display molecular layer disposed between the first substrate and the second substrate; an electrical shielding layer disposed on the first outer surface of the first substrate, wherein the electrical shielding layer comprises a first shielding region corresponding to the first color resist and a second shielding region corresponding to the bonding region.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 16, 2024
    Assignee: AU OPTRONICS (KUNSHAN) CO., LTD.
    Inventors: Yung Chuan Chu, Chao-Yun Cheng, Shan-Fang Chen, Haiyan Liu
  • Publication number: 20230422513
    Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.
    Type: Application
    Filed: June 25, 2022
    Publication date: December 28, 2023
    Inventors: Hung-Wei LI, Sai-Hooi YEONG, Chia-Ta YU, Chih-Yu CHANG, Wen-Ling LU, Yu-Chien CHIU, Ya-Yun CHENG, Mauricio MANFRINI, Yu-Ming LIN
  • Patent number: 11856783
    Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Chun Liou, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin, Chia-En Huang
  • Patent number: D1023010
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 16, 2024
    Assignee: Acer Incorporated
    Inventors: Yun Cheng, Tsun-Chih Yang
  • Patent number: D1024075
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Yun Cheng, Tsun-Chih Yang
  • Patent number: D1024474
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: April 23, 2024
    Inventor: Yun Cheng