Abstract: A method includes: forming an interconnect structure over a substrate, the forming of the interconnect structure includes forming a memory device including a transistor. The forming of the interconnect structure includes: forming a first metallization layer and a second metallization layer over the first metallization layer; forming a gate region of the transistor in at least one of the first and second metallization layers; etching a trench disposed in the second metallization layer and exposing the gate region; depositing a gate dielectric layer in the trench over the gate region; depositing a channel layer in the trench over the gate dielectric layer; and forming two source/drain regions of the transistor over the channel layer on opposite sides of the trench. At least one of the gate region and the channel layer includes two first segments extending in the trench, wherein the first segments are parallel with each other.

Abstract: An integrated wafer debonding and cleaning apparatus and a debonding and cleaning method are provided. The integrated wafer debonding and cleaning apparatus includes an input port, a debonding module, a wafer cleaning device, and a transport device. The input port is configured to allow a substrate to be processed to enter the integrated wafer debonding and cleaning apparatus. The substrate to be processed includes a wafer and a carrier which are bonded. The debonding module is configured to debond the substrate to be processed, and to separate the wafer from the carrier. The wafer cleaning apparatus is configured to clean the wafer. The transport device is configured to transfer the substrate to be processed, the wafer, and the carrier. The debonding module and the wafer cleaning module are integrated in one apparatus for continuous processing.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than 3/5.

Abstract: An embodiment of the invention provides a method for a location tracking, applied to a mobile device, an indoor access point (AP) and at least one indoor Internet of Things (IoT) device, comprising: receiving, by the indoor AP, a first set of location information of the mobile device from the mobile device at outdoor, wherein the first set of location information is determined according to a Global Navigation Satellite System (GNSS); determining, by the indoor AP, a second set of location information of the indoor AP according to the first set of location information; determining, by the indoor AP, a third set of location information of the at least one indoor IoT device according to the second set of location information; and transmitting, by the indoor AP, the third set of location information to the at least one indoor IoT device.

Abstract: Methods for speaker role determination and scrubbing identifying information are performed by systems and devices. In speaker role determination, data from an audio or text file is divided into respective portions related to speaking parties. Characteristics classifying the portions of the data for speaking party roles are identified in the portions to generate data sets from the portions corresponding to the speaking party roles and to assign speaking party roles for the data sets. For scrubbing identifying information in data, audio data for speaking parties is processed using speech recognition to generate a text-based representation. Text associated with identifying information is determined based on a set of key words/phrases, and a portion of the text-based representation that includes a part of the text is identified. A segment of audio data that corresponds to the identified portion is replaced with different audio data, and the portion is replaced with different text.

Abstract: A three-dimensional printer includes a projector, a tank, and a platform. The projector includes a light source, a digital micromirror device, and a controller. The digital micromirror device includes a micromirror, and the micromirror may be switched between an on state and an off state according to a control signal. The controller is electrically connected to the digital micromirror device and the light source. The controller further includes a judgement unit. The judgement unit may output the control signal to switch the micromirror to the off state when the light source is in the off state. The platform is adjacent to the tank. In addition, a manufacturing method for a three-dimensional printer is provided.

Abstract: A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.

Abstract: A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.

Abstract: The present invention relates to a display device, comprising: a first substrate comprising a first inner surface, a first outer surface opposite to the first inner surface, a display region, a bonding region adjacent to the display region, a plurality of thin film transistors disposed on the first inner surface and corresponding to the display region; a second substrate opposite to the display region and comprising a second inner surface, a second outer surface opposite to the second inner surface, a first color resist and a second color resist each disposed on the second inner surface; a display molecular layer disposed between the first substrate and the second substrate; an electrical shielding layer disposed on the first outer surface of the first substrate, wherein the electrical shielding layer comprises a first shielding region corresponding to the first color resist and a second shielding region corresponding to the bonding region.

Abstract: A memory cell includes a transistor and a capacitor. The transistor includes a gate electrode, a gate dielectric disposed over the gate electrode, a channel feature disposed over the gate dielectric and overlapping the gate electrode, a source electrode disposed over the channel feature and electrically connected to the capacitor, and two drain electrodes disposed over the channel feature. The drain electrodes are disposed at opposite sides of the source electrode. The channel feature has a first channel portion extending between and interconnecting one drain electrode and the source electrode, and a second channel portion extending between and interconnecting the other drain electrode and the source electrode. The gate electrode overlaps both of the first channel portion and the second channel portion of the channel feature.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: Aspects of the disclosure relate to methods and compositions for treatment of certain ocular diseases and disorders, for example age-related macular degeneration (AMD). In some embodiments, the methods comprise administering a subject having AMD one or more therapeutic agents that modulate the mTORCl pathway (or a component thereof). The disclosure is based, in part, on methods for treating AMD in a subject by administering one or more kinase inhibitors, for example one or more serine/threonine kinase inhibitors. In some embodiments, at least one of the serine/threonine kinase inhibitors is a Ribosomal protein S6 kinase beta-1 (S6K1) inhibitor.

Abstract: A ferroelectric memory device includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stack is disposed on a substrate and includes conductive layers and dielectric layers stacked alternately. The ferroelectric layer has a curvy profile and is disposed along sidewalls of the conducive layers and sidewalls of the dielectric layers. The channel layers are separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layers respectively.

Abstract: The present disclosure provides a circuit and a method thereof for setting an SDRAM. The circuit includes at least one register and a controller circuit. The controller circuit is configured to: control the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is utilized for initialing the SDRAM; set value of the at least one register under the initialization setting mode; and set the SDRAM according to the value of the at least one register.

Abstract: A foam and a foaming composition are provided. The foam includes a composite material and a plurality of foam cells, wherein the foam cells are disposed in the composite material. The composite material includes a modified sulfur-containing polymer and a fluorine-containing polymer fiber, wherein a degree of orientation as defined by the ratio I110/I200 is from 1.0 to 1.3, wherein I110 is the X-ray diffraction peak intensity of (110) planes of the modified sulfur-containing polymer and I200 is the X-ray diffraction peak intensity of (200) planes of the modified sulfur-containing polymer.

Abstract: The disclosure provides a touch panel and a touch device. The touch panel includes a touch film layer and a fingerprint identification film layer. The touch film layer includes at least one preset hollow. An orthographic projection of the fingerprint identification film layer on the touch film layer is located in at least one preset hollow area.

Abstract: An automatic sewage regulation system and a regulating method are provided. The automatic sewage regulation system is disposed between preset sewage sources and a preset sewage treatment apparatus and includes an equalization tank and an automatic sewage regulating device. The automatic sewage regulating device includes sensing modules for sensing and transmitting water quality sensing values of sewage in the preset sewage sources to a control module which outputs regulating signals to water flow regulators, so that the water flow regulators can regulate flowing volumes of the sewage of the preset sewage sources according to the regulating signal, to keep a water quality sensing value of the sewage in the equalization tank within a preset range, thereby preventing the equalization tank from converging sewage having excessively-high or excessively-low water quality sensing value. As a result, burden of a preset sewage treatment apparatus can be reduced.

Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.