Abstract: A light emitting display device including a substrate including first and second subpixels, a first insulating layer on the substrate, a first anode including first lower and upper electrodes on the first insulating layer at the first subpixel, a second anode including second lower and upper electrodes spaced from each other by the first insulating layer at the second subpixel, a first electrode pattern at non-emission areas and spaced from the first lower electrode, and a second electrode pattern spaced from the second lower electrode to overlap the first electrode pattern. A first vertical distance from an upper surface of the substrate to an upper surface of the first electrode pattern may be greater than a second vertical distance from the upper surface of the substrate to an upper surface of the first upper electrode.

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Abstract: Described is a method of coating the inside of an exhaust gas purification catalyst filter with a predetermined amount of catalyst slurry while adjusting the distribution of catalyst components in or on a cell wall of the filter. A predetermined amount of catalyst slurry can be injected into an internal channel of a filter to solve conventional problems caused by excess or surplus slurry injection. The predetermined amount of slurry injected into the internal channel of the filter is coated on or in the cell wall, depending on the viscosity and particle size of the slurry. This enables a coating profile in which the slurry distribution at a front portion of the filter and the slurry distribution at a back portion of the filter differ from each other.

Abstract: A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: A calibration apparatus includes a calibration circuit and a singularity detection (SD) circuit. The calibration circuit performs a calibration process upon a time-interleaved analog-to-digital converter (TI-ADC) with a plurality of TI channels, wherein the calibration process includes detecting and correcting mismatch between different TI channels of the TI-ADC. The SD circuit sets an SD flag by evaluating variation of statistical characteristics of an ADC input signal between different TI channels of the TI-ADC, and outputs the SD flag to the calibration circuit, wherein the calibration circuit controls the calibration process according to the SD flag.

Abstract: Various embodiments set forth eye tracking systems. In some embodiments, an eye tracking system includes a polarization volume hologram (PVH) combiner having a rolling k-vector design that provides relatively wide coverage of users whose eyeglasses prescriptions can vary. The PVH combiner can further include (1) fiducial regions created by differential patterning that generate dark regions in images captured of an eye, and/or (2) multiple regions that diffract light at angles to produce different perspectives in the captured images. The dark regions and/or different perspectives can be used to calibrate eye tracking. In addition, the PVH combiner can include off-axis lens regions that generate glints for the eye tracking.

Abstract: A restructurable hybrid-wing VTOL aircraft includes a fuselage, two wings, two canard wings and a cabin door. The two wings are provided to opposite sides of the fuselage. Each the wing is provided vertically and symmetrically by two rotary wing modules, and thus an H configuration to the fuselage can be formed. While the lower rotary wing module rotates to align the corresponding wing, a change of relative position with respect to the upper rotary wing module can be generated. Through the rotation of the lower rotary wing module, the vertical surface thereof would be transformed into a lift surface for enlarging the aspect ratio of the wing to improve the corresponding lift-drag ratio. Thereupon, a disadvantage of hyper flight-directional stability to the H-configured tail seat-type aircraft caused by the vertical area of the aircraft can be reduced, and so the tail-seat type aircraft can slide to emergency land.

Abstract: A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

Abstract: Methods are provided herein for patterning extreme ultraviolet (EUV) (or lower wavelength) photoresists, such metal-oxide photoresists. A patterning layer comprising a metal-oxide photoresist is provided on one or more underlying layers provided on a substrate, and portions of the patterning layer not covered by a mask overlying the patterning layer are exposed to EUV or lower wavelengths light. A cyclic dry process is subsequently performed to remove portions of the patterning layer defined by the EUV or lower wavelength light and develop the metal-oxide photoresist pattern.

Abstract: A novel diamine compound and a low dielectric constant polyimide film based thereon are disclosed.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Abstract: A system includes a display element configured to output an image light. The system also includes an image combiner configured to guide the image light toward an eye-box region of the system. The system also includes a dimming device disposed at a side of the image combiner. The dimming device includes a dimming material layer including a mixture of liquid crystal (“LC”) molecules and dye molecules, and pretilt angles of the LC molecules and the dye molecules are configured with a predetermined variation in at least two opposite in-plane directions from a center to two opposite peripheries of the dimming material layer.

Abstract: A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Abstract: A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Abstract: A display device includes a display panel. An input sensor is disposed on the display panel. A first pattern of the input sensor includes mesh lines. A second pattern of the input sensor overlaps the first pattern with an insulating layer interposed therebetween, and includes mesh lines. The mesh lines of the first pattern include a first mesh line extending in the first reference direction, and the mesh lines of the second pattern include a second mesh line extending in the first reference direction and overlapping the first mesh line in a plan view. In a plan view, first cutting areas in which the first mesh line is partially cut and second cutting areas in which the second mesh line is partially cut do not overlap.

Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Abstract: A device includes a display configured to generate an image light. The device also includes a waveguide optically coupled with the display and configured to guide the image light to an exit pupil of the device. The waveguide includes a grating including a birefringent material, and a birefringence of the grating is configured to increase along a pupil-expanding direction of the device.