Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A method and a system for mental index prediction are provided. The method includes the following steps. A plurality of images of a subject person are obtained. A plurality of emotion tags of the subject person in the images are analyzed. A plurality of integrated emotion tags in a plurality of predetermined time periods are calculated according to the emotion tags respectively corresponding to the images. A plurality of preferred features are determined according to the integrated emotion tags. A mental index prediction model is established according to the preferred features to predict a mental index according to the emotional index prediction model.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: Presented herein is a stage area for “focused” video that is configured to allow for dynamic layout changes during an online video conference or meeting. By providing a user interface environment that allows a user (meeting participant) to customize the stage, each participant can choose their own view, and the meeting host can fully customize a view for every participant in the meeting.

Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: A display device and a method of manufacturing the same are provided. The display device, comprises a first base substrate, a first barrier layer disposed on the first base substrate, a second base substrate disposed on the first barrier layer, at least one transistor disposed on the second base substrate, and an organic light emitting diode disposed on the at least one transistor, wherein the first barrier layer includes a silicon oxide, and has an adhesion force of 200 gf/inch or more to the second base substrate.

Abstract: A method for plasma processing includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first radio frequency (RF) electrode and a second RF electrode, where sustaining the plasma includes: coupling an RF source signal to the first RF electrode; and coupling a bias signal between the first RF electrode and the second RF electrode, the bias signal having a bipolar DC (B-DC) waveform including a plurality of B-DC pulses, each of the B-DC pulses including: a negative bias duration during which the pulse has negative polarity relative to a reference potential, a positive bias duration during which the pulse has positive polarity relative to the reference potential, and a neutral bias duration during which the pulse has neutral polarity relative to the reference potential.

Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Abstract: A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. The integrated circuit design corresponding to the integrated circuit. The performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. The heat signature includes heat values distributed throughout the integrated circuit design.

Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.

Abstract: A method for protecting sensitive data from being exposed in graph embedding vectors. In some embodiments, a method may include generating first graph embedding vectors from an original graph and generating a proxy graph from the first graph embedding vectors. The proxy graph may include a plurality of proxy nodes and proxy edges connecting the proxy nodes. The proxy nodes may include one or more attributes of the original nodes that are included in the first graph embedding vectors. Second graph embedding vectors may then be generated by encoding the proxy graph and a reconstructed graph may be generated from the second graph embedding vectors. Finally, the reconstructed graph may be compared to the original graph and if a threshold level of similarity is met, a security action may be performed to protect sensitive data from being exposed.

Abstract: The present invention relates to an E. coli hisG-derived ATP-phosphoribosyltransferase variant having a reduced feedback inhibition by histidine and a strain expressing the same. The variant may maintain its activity even at a high histidine concentration, thus increasing histidine production.

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.