Abstract: A console module disclosed includes a case positioned below a dashboard of a vehicle, and a connection portion configured to connect the case to the dashboard, allowing the case, positioned below the dashboard, to move between a non-use position and a use position, in which the case protrudes further rearward than in the non-use position.

Abstract: A method includes providing a workpiece in an etching apparatus at ambient temperature, the workpiece comprising a dielectric layer adjacent a conductive layer over a semiconductor substrate. The method includes performing an etching process to selectively remove the dielectric layer relative to the conductive layer. The method further includes, while performing the etching process, cooling the workpiece to a processing temperature that is below the ambient temperature.

Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.

Abstract: A voltage regulator includes a power supply voltage node, a power supply reference node, an output node, a plurality of phase circuits, and a control circuit. Each phase circuit of the plurality of phase circuits includes at least one p-type transistor coupled to the power supply voltage node, at least one n-type transistor coupled to the power supply reference node, and an inductor including a first terminal coupled exclusively to the at least one p-type transistor and the at least one n-type transistor, and a second terminal coupled to the output node. The control circuit is configured to, responsive to a power state signal, enable a predetermined number of phase circuits of the plurality of phase circuits, and the inductors of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and include a same inductor type.

Abstract: A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Abstract: A liquid crystal display (LCD) system for a head mounted display includes an LCD panel and a backlight unit. The LCD panel includes a color filter on array (COA) configuration. The backlight unit includes a light adjustment layer to adjust at least one characteristic of illumination light from a light source to tune the illumination light for enlarging an emission cone of display light.

Abstract: A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

Abstract: A method for patterning includes having a substrate including a first layer, a second layer to-be-patterned disposed under the first layer, and a third layer disposed under the second layer, the first layer including a plurality of lines, each of the plurality of lines being separated by a recess, a bottom of the recess exposing a surface of the second layer; exposing the substrate to a first plasma to extend the recesses through the second layer to expose a surface of the third layer, the first plasma being generated from a first halogen based gas and a first oxidizing gas, the first halogen based gas including a carbon-containing halogen based gas; and laterally etching the recesses in the second layer using a second plasma, the second plasma being generated from a second halogen based gas and a second oxidizing gas, the second halogen based gas being a carbon-free halogen based gas.

Abstract: A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

Abstract: A system includes a light outputting element configured to output a first beam propagating toward a beam interference zone from a first side of the beam interference zone. The system also includes a reflective assembly configured to reflect the first beam back as a second beam propagating toward the beam interference zone from a second side of the beam interference zone. The first beam and the second beam interfere with one another within the beam interference zone to generate a polarization interference pattern.

Abstract: The disclosed device may include a waveguide; an output coupler that couples electromagnetic radiation from within the waveguide to outside of the waveguide; and a reflector positioned on an opposite side of the waveguide from the output coupler, where the reflector reflects electromagnetic radiation that leaks from the waveguide through the opposite side of the waveguide back toward the output coupler. Various other devices, systems, and methods are also disclosed.

Abstract: An optical element includes a waveguide body that is configured to guide light by total internal reflection from an input end to an output end, an input coupling element located at the input end for coupling light into the waveguide body, and an output coupling element located at the output end for coupling light out of the waveguide body, where the waveguide body includes an organic solid crystal. The organic solid crystal may be a single crystal having principal axes rotated with respect to the dimensions of the waveguide body. Such an optical element may have low weight and exhibit good color uniformity while providing polarization scrambling of the guided light.

Abstract: A light emitting display device including a substrate including first and second subpixels, a first insulating layer on the substrate, a first anode including first lower and upper electrodes on the first insulating layer at the first subpixel, a second anode including second lower and upper electrodes spaced from each other by the first insulating layer at the second subpixel, a first electrode pattern at non-emission areas and spaced from the first lower electrode, and a second electrode pattern spaced from the second lower electrode to overlap the first electrode pattern. A first vertical distance from an upper surface of the substrate to an upper surface of the first electrode pattern may be greater than a second vertical distance from the upper surface of the substrate to an upper surface of the first upper electrode.

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Abstract: Described is a method of coating the inside of an exhaust gas purification catalyst filter with a predetermined amount of catalyst slurry while adjusting the distribution of catalyst components in or on a cell wall of the filter. A predetermined amount of catalyst slurry can be injected into an internal channel of a filter to solve conventional problems caused by excess or surplus slurry injection. The predetermined amount of slurry injected into the internal channel of the filter is coated on or in the cell wall, depending on the viscosity and particle size of the slurry. This enables a coating profile in which the slurry distribution at a front portion of the filter and the slurry distribution at a back portion of the filter differ from each other.

Abstract: A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: A calibration apparatus includes a calibration circuit and a singularity detection (SD) circuit. The calibration circuit performs a calibration process upon a time-interleaved analog-to-digital converter (TI-ADC) with a plurality of TI channels, wherein the calibration process includes detecting and correcting mismatch between different TI channels of the TI-ADC. The SD circuit sets an SD flag by evaluating variation of statistical characteristics of an ADC input signal between different TI channels of the TI-ADC, and outputs the SD flag to the calibration circuit, wherein the calibration circuit controls the calibration process according to the SD flag.