Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.

Abstract: A voltage regulator includes a power supply voltage node, a power supply reference node, an output node, a plurality of phase circuits, and a control circuit. Each phase circuit of the plurality of phase circuits includes at least one p-type transistor coupled to the power supply voltage node, at least one n-type transistor coupled to the power supply reference node, and an inductor including a first terminal coupled exclusively to the at least one p-type transistor and the at least one n-type transistor, and a second terminal coupled to the output node. The control circuit is configured to, responsive to a power state signal, enable a predetermined number of phase circuits of the plurality of phase circuits, and the inductors of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and include a same inductor type.

Abstract: A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Abstract: A liquid crystal display (LCD) system for a head mounted display includes an LCD panel and a backlight unit. The LCD panel includes a color filter on array (COA) configuration. The backlight unit includes a light adjustment layer to adjust at least one characteristic of illumination light from a light source to tune the illumination light for enlarging an emission cone of display light.

Abstract: A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

Abstract: A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

Abstract: A system includes a light outputting element configured to output a first beam propagating toward a beam interference zone from a first side of the beam interference zone. The system also includes a reflective assembly configured to reflect the first beam back as a second beam propagating toward the beam interference zone from a second side of the beam interference zone. The first beam and the second beam interfere with one another within the beam interference zone to generate a polarization interference pattern.

Abstract: An optical element includes a waveguide body that is configured to guide light by total internal reflection from an input end to an output end, an input coupling element located at the input end for coupling light into the waveguide body, and an output coupling element located at the output end for coupling light out of the waveguide body, where the waveguide body includes an organic solid crystal. The organic solid crystal may be a single crystal having principal axes rotated with respect to the dimensions of the waveguide body. Such an optical element may have low weight and exhibit good color uniformity while providing polarization scrambling of the guided light.

Abstract: The disclosed device may include a waveguide; an output coupler that couples electromagnetic radiation from within the waveguide to outside of the waveguide; and a reflector positioned on an opposite side of the waveguide from the output coupler, where the reflector reflects electromagnetic radiation that leaks from the waveguide through the opposite side of the waveguide back toward the output coupler. Various other devices, systems, and methods are also disclosed.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: Various embodiments set forth eye tracking systems. In some embodiments, an eye tracking system includes a polarization volume hologram (PVH) combiner having a rolling k-vector design that provides relatively wide coverage of users whose eyeglasses prescriptions can vary. The PVH combiner can further include (1) fiducial regions created by differential patterning that generate dark regions in images captured of an eye, and/or (2) multiple regions that diffract light at angles to produce different perspectives in the captured images. The dark regions and/or different perspectives can be used to calibrate eye tracking. In addition, the PVH combiner can include off-axis lens regions that generate glints for the eye tracking.

Abstract: A system includes a display element configured to output an image light. The system also includes an image combiner configured to guide the image light toward an eye-box region of the system. The system also includes a dimming device disposed at a side of the image combiner. The dimming device includes a dimming material layer including a mixture of liquid crystal (“LC”) molecules and dye molecules, and pretilt angles of the LC molecules and the dye molecules are configured with a predetermined variation in at least two opposite in-plane directions from a center to two opposite peripheries of the dimming material layer.

Abstract: A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Abstract: A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Abstract: A device includes a display configured to generate an image light. The device also includes a waveguide optically coupled with the display and configured to guide the image light to an exit pupil of the device. The waveguide includes a grating including a birefringent material, and a birefringence of the grating is configured to increase along a pupil-expanding direction of the device.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Abstract: A liquid crystal display (LCD) system for a head mounted display includes an LCD panel and a backlight unit. The LCD panel includes a color filter on array (COA) configuration. The backlight unit includes a light adjustment layer to adjust at least one characteristic of illumination light from a light source to tune the illumination light for enlarging an emission cone of display light.

Abstract: A liquid crystal pixel includes liquid crystals, a source electrode, and a transparent common electrode layer. The liquid crystals are configured to change an alignment of the liquid crystals in response to a voltage applied across the source electrode and the transparent common electrode layer. The slit in the transparent common electrode layer includes multiple angled sections.

Abstract: A non-transitory computer-readable storage medium is encoded with a set of instructions for designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications that, when executed by at least one processor, cause the at least one processor to: retrieve a source code operable to execute a plurality of operations of a machine learning algorithm; classify a first group of the plurality of operations as slow group operations and classify a second group of the plurality of operations as fast group operations, based on a time required to complete each operation; define a neural network operable to execute the slow group operations; define a trained neural network configuration including a plurality of interconnected neurons operable to execute the slow group operations; and generate an ESL platform for evaluating a design of a semiconductor device based on the trained neural network configuration.