Patents by Inventor Yun-Han Lee

Yun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210103180
    Abstract: An optical element includes a first boundary layer and a second boundary layer. A solution is disposed between the first boundary layer and the second boundary layer. The solution includes liquid crystals co-mingled with oblong photochromic dye molecules.
    Type: Application
    Filed: April 21, 2020
    Publication date: April 8, 2021
    Inventors: Jasmine Soria Sears, Afsoon Jamali, Yun-Han Lee
  • Patent number: 10969675
    Abstract: An optical assembly includes a first optical waveguide, a first in-coupler coupled with the first optical waveguide and a projector configured to project image light toward a first side of the first optical waveguide. The optical assembly also includes a first scanning reflector optically coupled with the projector and disposed on a second side of the first optical waveguide that is opposite to the first side. The projector is configured to project image light. The first scanning reflector is configured to receive the image light and to redirect the image light across a first range of directions. The first in-coupler is configured to redirect a first portion of the image light so that the first portion of the image light undergoes total internal reflection inside the first optical waveguide.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 6, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Brian Wheelwright, Yun-Han Lee, Babak Amirsolaimani, Weichuan Gao
  • Publication number: 20210096453
    Abstract: An optical assembly for projecting light from a display includes a first optical waveguide, a reflective optical element configured, and a first in-coupler. The reflective optical element is configured to receive first light having first polarization from the display and to reflect the first light as second light having second polarization distinct from the first polarization. The first in-coupler is coupled with the first optical waveguide. The first in-coupler is configured to receive and transmit the first light. The first in-coupler is further configured to receive the second light and redirect a first portion of the second light so that the first portion of the second light undergoes total internal reflection inside the first optical waveguide.
    Type: Application
    Filed: June 10, 2019
    Publication date: April 1, 2021
    Inventors: Brian WHEELWRIGHT, Yun-Han LEE, Babak AMIRSOLAIMANI, Weichuan GAO
  • Publication number: 20210089696
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group and/or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing the slow operation group operation on the machine learning hardware configuration, finalizing the machine learning hardware configuration capable of successfully executing least one test data set.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Patent number: 10922466
    Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
  • Publication number: 20210033770
    Abstract: A first layer of anisotropic material extends along a first plane and includes anisotropic components being parallel to a second plane non-parallel and non-perpendicular to the first plane. The anisotropic components are arranged in cycloidal or helical patterns. The cycloidal or helical patterns define one or more Bragg planes that are non-parallel and non-perpendicular to the first plane and either substantially parallel or substantially perpendicular to the second plane.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Lu LU, Xiayu FENG, Mengfei WANG, Hao YU, Ryan LI, Yun-Han LEE, Junren WANG, Barry David SILVERSTEIN
  • Patent number: 10890778
    Abstract: An optical system includes a grating including at least one substrate and a grating structure coupled to the at least one substrate. The grating structure is configured to diffract a first light having an incidence angle within a predetermined range. The optical system also includes a polarizer configured to transmit the first light diffracted by the grating structure and block a second light reflected by a surface of the at least one substrate.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 12, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Yun-Han Lee, Mengfei Wang, Junren Wang, Lu Lu, Robin Sharma, Gregory Olegovic Andreev, Garam Young, Andrew John Ouderkirk, Babak Amirsolaimani, Fenglin Peng, Barry David Silverstein
  • Publication number: 20200410144
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Yun-Han LEE, Mei WONG, Hsin-Cheng CHEN
  • Patent number: 10871518
    Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Ankita Patidar
  • Publication number: 20200393690
    Abstract: An optical system includes a grating including at least one substrate and a grating structure coupled to the at least one substrate. The grating structure is configured to diffract a first light having an incidence angle within a predetermined range. The optical system also includes a polarizer configured to transmit the first light diffracted by the grating structure and block a second light reflected by a surface of the at least one substrate.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Yun-Han LEE, Mengfei WANG, Junren WANG, Lu LU, Robin SHARMA, Gregory Olegovic ANDREEV, Garam YOUNG, Andrew John OUDERKIRK, Babak AMIRSOLAIMANI, Fenglin PENG, Barry David SILVERSTEIN
  • Patent number: 10867089
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Charlie Zhou, Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Patent number: 10867098
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Publication number: 20200381392
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Publication number: 20200379013
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Publication number: 20200372124
    Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing operations of the slow operation group on the initial machine learning hardware configuration, modifying the initial machine learning hardware configuration in response to a determination that the slow group operation fails to produce an expected result in response to at least one set of inputs; and executing a fast group operation using a machine learning software code.
    Type: Application
    Filed: September 25, 2019
    Publication date: November 26, 2020
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Publication number: 20200321248
    Abstract: The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20200311329
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20200304133
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 10782318
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 10776538
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Mei Wong, Hsin-Cheng Chen