Patents by Inventor Yun-Han Lee

Yun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9811627
    Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chin Hou, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20170307683
    Abstract: A bi-directional scan chain includes a plurality of cell structures, each cell structure having a storage device and at least one multiplexer, the plurality of cell structures coupled to one another in a series configuration, wherein an output of a (K-1)-th cell structure is provided as input to the K-th cell structure to provide a forward data shifting operation, and an output of the K-th cell structure is provided as an input to the (K-1)-th cell structure to provide a backward data shifting operation, where K is an integer greater than 1.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 26, 2017
    Applicant: Taiwan Semiconductor Manufacturing Col, Ltd
    Inventors: Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20170300607
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Application
    Filed: July 3, 2017
    Publication date: October 19, 2017
    Inventors: Yun-Han Lee, Wu-An Kuo
  • Publication number: 20170300604
    Abstract: A method of estimating power consumption for a system on chip (SOC) includes simulating operation of a first sub-block to obtain power consumption information for the first sub-block including first activation information for a first IP block. The method further includes simulating operation of a second sub-block to obtain power consumption information for the second sub-block including second activation information for the first IP block and activation information for a plurality of second IP blocks. The method further includes determining a weighting factor for the first activation information for the first IP block, the second activation information for the first IP block and the activation information for each second IP block. The method further includes estimating power consumption for the SOC based on the first and second activation information for the first IP block, the activation information for at least one second IP block, and corresponding weighting factors.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: Shereef SHEHATA, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE, Mei WONG
  • Patent number: 9779990
    Abstract: Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20170221858
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 9704766
    Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Mill-Jer Wang, Chung-Sheng Yuan, Tom Chen, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 9697319
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Wu-An Kuo
  • Patent number: 9686865
    Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Mark Shane Peng, Shyh-An Chi
  • Publication number: 20170161420
    Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 8, 2017
    Inventors: Yung-Chin HOU, Sandeep Kumar GOEL, Yun-Han LEE
  • Patent number: 9647028
    Abstract: A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20170117932
    Abstract: An integrated circuit includes a first radio frequency interconnect (RFI) transceiver, a second RFI transceiver, a third RFI transceiver, a fourth RFI transceiver and a guided transmission medium. The first RFI transceiver is configured to transmit or receive a first data signal. The second RFI transceiver is configured to transmit or receive a second data signal. The third RFI transceiver is configured to transmit or receive the first data signal. The fourth RFI transceiver is configured to transmit or receive the second data signal. The guided transmission medium is configured to carry the first data signal and the second data signal. The first RFI transceiver and the second RFI transceiver are connected to the third RFI transceiver and the fourth RFI transceiver by the guided transmission medium.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Inventors: Huan-Neng CHEN, William Wu SHEN, Chewn-Pu JOU, Feng Wei KUO, Lan-Chou CHO, Tze-Chiang HUANG, Jack LIU, Yun-Han LEE
  • Patent number: 9633147
    Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Stanley John, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Publication number: 20170111193
    Abstract: A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: HUAN-NENG CHEN, WILLIAM WU SHEN, LAN-CHOU CHO, FENG WEI KUO, CHEWN-PU JOU, TZE-CHIANG HUANG, JACK LIU, YUN-HAN LEE
  • Patent number: 9627365
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Publication number: 20170098023
    Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 6, 2017
    Inventors: STANLEY JOHN, SANDEEP KUMAR GOEL, TZE-CHIANG HUANG, YUN-HAN LEE
  • Patent number: 9613174
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Publication number: 20170083654
    Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
  • Publication number: 20170076029
    Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 16, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tze-Chiang HUANG, Kai-Yuan TING, Sandeep Kumar GOEL, Yun-Han LEE, Shereef SHEHATA, Mei WONG
  • Publication number: 20170076028
    Abstract: A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.
    Type: Application
    Filed: July 1, 2016
    Publication date: March 16, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE