Patents by Inventor Yun-Han Lee

Yun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180314772
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of a various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Charlie ZHOU, Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Patent number: 10115327
    Abstract: An optical display system includes an information display (image-generating) component, a polarization dependent image offset optical element and possibly also a polarization rotator. By controlling the image offset optical element either by direct applying voltage or by controlling the polarization of the displayed light through the polarization rotator, the display pixels can be switched by a certain portion. By switching between offset and non-offset state with appropriate image displayed, the resolution as observed by the users can be enhanced.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 30, 2018
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Yun-Han Lee, Tao Zhan, Guanjun Tan, Fangwang Gou, Fenglin Peng, Shin-Tson Wu
  • Patent number: 10108764
    Abstract: A method of estimating power consumption for a system on chip (SOC) includes simulating operation of a first sub-block to obtain power consumption information for the first sub-block including first activation information for a first IP block. The method further includes simulating operation of a second sub-block to obtain power consumption information for the second sub-block including second activation information for the first IP block and activation information for a plurality of second IP blocks. The method further includes determining a weighting factor for the first activation information for the first IP block, the second activation information for the first IP block and the activation information for each second IP block. The method further includes estimating power consumption for the SOC based on the first and second activation information for the first IP block, the activation information for at least one second IP block, and corresponding weighting factors.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shereef Shehata, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee, Mei Wong
  • Patent number: 10101796
    Abstract: A method of estimating power consumption of a processor includes accessing an electronic system level (ESL) model of the processor, the ESL model including a plurality of functional blocks, identifying a plurality of processor events by tracing activity of the plurality of functional blocks for a plurality of machine code instructions, and calculating a first power consumption value based on the plurality of processor events. The method also includes identifying a plurality of cycles by analyzing a plurality of micro-code operation codes corresponding to the plurality of machine code instructions, calculating a second power consumption value based on the plurality of cycles, and calculating a total power consumption value from the first power consumption value summed with the second power consumption value.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Publication number: 20180268096
    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.
    Type: Application
    Filed: October 4, 2017
    Publication date: September 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Wei-Li CHEN, Wei-Pin CHANGCHIEN, Yung-Chin HOU, Yun-Han LEE
  • Patent number: 10078720
    Abstract: Systems and methods for circuit fault diagnosis are provided. An original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on one or more first faults. In response to the original circuit design being determined not to be modified based at least in part on the one or more first faults, a first test pattern set is automatically generated based at least in part on the original circuit design. The original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on the first test pattern set. In response to the original circuit design being determined not to be modified based at least in part on the first test pattern set, fault testing is performed to determine whether the original circuit design fails.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sandeep Kumar Goel, Zipeng Li, Yun-Han Lee
  • Publication number: 20180164369
    Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
    Type: Application
    Filed: May 23, 2017
    Publication date: June 14, 2018
    Inventors: Sandeep Kumar GOEL, Stanley JOHN, Ji-Jan CHEN, Yun-Han LEE
  • Publication number: 20180149698
    Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.
    Type: Application
    Filed: May 11, 2017
    Publication date: May 31, 2018
    Inventors: Sandeep Kumar GOEL, Abhishek KONERU, Tri NGO, Yun-Han LEE
  • Publication number: 20180152193
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Publication number: 20180069807
    Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: RAVI VENUGOPALAN, SANDEEP KUMAR GOEL, YUN-HAN LEE
  • Publication number: 20180038894
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 8, 2018
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 9887863
    Abstract: A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, William Wu Shen, Lan-Chou Cho, Feng Wei Kuo, Chewn-Pu Jou, Tze-Chiang Huang, Jack Liu, Yun-Han Lee
  • Publication number: 20180012799
    Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 11, 2018
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20170350939
    Abstract: A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 7, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I. ADHAM, Marat GERSHOIG
  • Patent number: 9835680
    Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham
  • Publication number: 20170344093
    Abstract: A power state transformer, a system and a method thereof are disclosed. The power state transformer is coupled with a processing unit model. The power state transformer is configured for counting performance activities executed in the processing unit model, and further for determining a power state of the processing unit model according to count values of the performance activities.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yuan TING, Shereef SHEHATA, Tze-Chiang HUANG, Sandeep Kumar GOEL, Mei WONG, Yun-Han LEE
  • Publication number: 20170344091
    Abstract: A method of estimating power consumption of a processor includes accessing an electronic system level (ESL) model of the processor, the ESL model including a plurality of functional blocks, identifying a plurality of processor events by tracing activity of the plurality of functional blocks for a plurality of machine code instructions, and calculating a first power consumption value based on the plurality of processor events. The method also includes identifying a plurality of cycles by analyzing a plurality of micro-code operation codes corresponding to the plurality of machine code instructions, calculating a second power consumption value based on the plurality of cycles, and calculating a total power consumption value from the first power consumption value summed with the second power consumption value.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Tze-Chiang HUANG, Yun-Han LEE
  • Patent number: 9830413
    Abstract: A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Patent number: 9817029
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 9811627
    Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chin Hou, Sandeep Kumar Goel, Yun-Han Lee