Abstract: A system includes a diffractive optical element configured to receive a first beam and a second beam interfering with one another to generate a first interference pattern. The diffractive optical element is also configured to forwardly diffract the first beam and the second beam to output a third beam and a fourth beam. The third beam and the fourth beam interfere with one another to generate a second interference pattern. The system also includes a detector configured to detect the second interference pattern.

Abstract: A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Abstract: The disclosed optical assembly may include a photoalignment layer that includes photoalignment material (PAM) anchored to a substrate according to a specified surface anchoring. The optical assembly may also include a functional or transforming layer that is applied to the photoalignment layer. The transforming layer may modify the surface anchoring of the photoalignment layer to align with a polarization volume hologram layer. The polarization volume hologram layer of the optical assembly may be disposed on the transforming layer. Various other methods of manufacturing, systems, and apparatuses are also disclosed.

Abstract: A micro-light emitting diode device includes a backplane including drive circuits formed thereon, an array of micro-LEDs bonded to the backplane and electrically coupled to the drive circuits, an array of polarization diffraction micro-lenses bonded to the array of micro-LEDs and including a planar surface, and a cover glass bonded to the planar surface of the array of polarization diffraction micro-lenses. A center of each polarization diffraction micro-lens of the array of polarization diffraction micro-lenses aligns with a center of a respective micro-LED of the array of micro-LEDs.

Abstract: A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: A device is provided. The device includes a polarization hologram polymer layer having a wavy surface, an optic axis of the polarization hologram polymer layer being configured with a spatially varying orientation in a first predetermined in-plane direction. The device also includes a compensation layer disposed at the wavy surface of the polarization hologram polymer layer and configured to compensate for the wavy surface in shape.

Abstract: A display device with a transparent illuminator and an liquid crystal (LC) display panel is disclosed. The transparent illuminator includes a light source and a transparent lightguide, which may be based on a slab of transparent material with zigzag light propagation of the illuminating light in the slab and/or a transparent photonic integrated circuit with singlemode ridge waveguides for spreading the illuminating light in a plane parallel to the plane of LC display panel. The lightguide includes a plurality of grating out-couplers whose position is coordinated with positions of LC pixels for higher throughput. A reflective offset-to-angle optical element may be provided to form an image in angular domain through the LC panel and through the transparent illuminator, resulting in an overall compact and efficient display configuration.

Abstract: An optical element includes a first birefringent medium layer with orientations of directors of first optically anisotropic molecules spatially varying with a first in-plane pitch and a first vertical pitch. The optical element also includes a second birefringent medium layer with orientations of directors of second optically anisotropic molecules spatially varying with a second in-plane pitch and a second vertical pitch. The second birefringent medium layer is optically coupled with the first birefringent medium layer and configured to reduce a diffraction of a light by the first birefringent medium layer. The first in-plane pitch is substantially the same as the second in-plane pitch, and the second vertical pitch is smaller than the first vertical pitch.

Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.

Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.

Abstract: A system includes a light outputting element configured to output a first beam propagating toward a beam interference zone from a first side of the beam interference zone. The system also includes a wavefront shaping assembly disposed at a second side of the beam interference zone and including a polarization hologram, the wavefront shaping assembly being configured to reflect the first beam as a second beam propagating toward the beam interference zone from the second side. The first beam and the second beam are linearly polarized beams, and are configured to interfere with one another within the beam interference zone to generate an interference pattern that is recordable in a recording medium layer disposed in the beam interference zone.

Abstract: A system is provided. The system includes a light source configured to emit an infrared light to illuminate an eye of a user. The system includes a grating disposed facing the eye and including a birefringent material film configured with a uniform birefringence lower than or equal to 0.1. The grating is configured to diffract the infrared light reflected from the eye, and transmit a visible light from a real world environment toward the eye, with a diffraction efficiency less than a predetermined threshold. The system includes an optical sensor configured to receive the diffracted infrared light and generate an image of the eye based on the diffracted infrared light.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Abstract: A polarization conversion device includes a geometric phase grating and an angular selective waveplate. The geometric phase grating includes a first liquid crystal layer and is configured to diffract a unpolarized or partially polarized incident light beam into a first light beam and a second light beam (e.g., in two different diffraction orders). The first light beam is characterized by a first polarization state and propagates in a first direction. The second light beam is characterized by a second polarization state and propagates in a second direction. The angular selective waveplate includes a second liquid crystal layer, and functions as a zero or full-wave plate for the first light beam incident in the first direction and a half-wave plate for the second light beam incident in the second direction.

Abstract: A device is provided. The device includes a polarization hologram polymer layer having a wavy surface, an optic axis of the polarization hologram polymer layer being configured with a spatially varying orientation in a first predetermined in-plane direction. The device also includes a compensation layer disposed at the wavy surface of the polarization hologram polymer layer and configured to compensate for the wavy surface in shape.