Patents by Inventor Yun-Han Lee

Yun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11635624
    Abstract: A device includes a light guide and at least one in-coupling element configured to couple an image light into the light guide. The device also includes a first out-coupling element configured to couple a first portion of the image light out of the light guide as a plurality of first output lights. The device further includes a second out-coupling element spaced apart from the first out-coupling element by a distance and configured to couple a second portion the image light out of the light guide as a plurality of second output lights. The second output lights are substantially non-overlapping with the first output lights.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 25, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Babak Amirsolaimani, Scott Charles McEldowney, Yun-Han Lee, Lu Lu
  • Patent number: 11635669
    Abstract: A device includes a first substrate and a second substrate. The device also includes a birefringent medium layer disposed between the first substrate and the second substrate. Orientations of directors of optically anisotropic molecules included in the birefringent medium layer varying periodically with an in-plane pitch tunable by an external field to adjust a diffraction angle of a light beam diffracted by the birefringent medium layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 25, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Lu Lu, Hao Yu, Mengfei Wang, Junren Wang, Yun-Han Lee, Nicholas John Diorio, Barry David Silverstein
  • Patent number: 11632048
    Abstract: A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu, Yun-Han Lee
  • Publication number: 20230113905
    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I. ADHAM, Marat GERSHOIG
  • Patent number: 11624922
    Abstract: An optical assembly for projecting light output by a display includes an optical waveguide, a reflective optical element, and a in-coupler coupled with the optical waveguide. The reflective optical element is positioned to receive first light and to reflect the first light as second light. The in-coupler is positioned to receive the first light and transmit the first light toward the reflective optical element. The in-coupler is further positioned to receive the second light and redirect a first portion of the second light so that the first portion of the second light undergoes total internal reflection inside the optical waveguide. The reflective optical element includes a negative meniscus lens having a concave lens surface and a convex lens surface coupled with a reflective surface. The reflective optical element is positioned to focus the first light such that the second light is more collimated than the first light.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: April 11, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Brian Wheelwright, Yun-Han Lee, Babak Amirsolaimani, Weichuan Gao
  • Patent number: 11624864
    Abstract: An optical element is provided. The optical element includes an optical film including a birefringent material having a chirality. Optically anisotropic molecules of the birefringent material disposed adjacent a first surface of the optical film are configured with a first pretilt angle in a range of greater than 10° and less than 80°, or in a range of greater than ?80° and less than ?10°. Optically anisotropic molecules of the birefringent material disposed adjacent a second surface of the optical film opposing the first surface are configured with a second pretilt angle in the range of greater than 10° and less than 80°, or in the range of greater than ?80° and less than ?10°.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: April 11, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Junren Wang, Lu Lu, Hyunmin Song, Yun-Han Lee
  • Patent number: 11624913
    Abstract: An optical display system includes an information display (image-generating) component, a polarization dependent image offset optical element and possibly also a polarization rotator. By controlling the image offset optical element either by direct applying voltage or by controlling the polarization of the displayed light through the polarization rotator, the display pixels can be switched by a certain portion. By switching between offset and non-offset state with appropriate image displayed, the resolution as observed by the users can be enhanced.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 11, 2023
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Yun-Han Lee, Tao Zhan, Guanjun Tan, Fangwang Gou, Fenglin Peng, Shin-Tson Wu
  • Patent number: 11619774
    Abstract: An illuminator for a display panel includes a light source for providing a light beam and a lightguide coupled to the light source for receiving and propagating the light beam along the substrate. The lightguide includes an array of out-coupling gratings that runs parallel to the array of pixels for out-coupling portions of the light beam from the lightguide such that the out-coupled light beam portions propagate through the substrate and produce an array of optical power density peaks at the array of pixels due to Talbot effect. A period of the array of peaks is an integer multiple of a pitch of the array of pixels.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 4, 2023
    Assignee: Meta Platforms Technologies LLC
    Inventors: Jacques Gollier, Fenglin Peng, Alexander Koshelev, Giuseppe Calafiore, Lu Lu, Ying Geng, Yun-Han Lee
  • Patent number: 11616631
    Abstract: An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Neng Chen, William Wu Shen, Chewn-Pu Jou, Feng Wei Kuo, Lan-Chou Cho, Tze-Chiang Huang, Jack Liu, Yun-Han Lee
  • Publication number: 20230080580
    Abstract: A device includes a diffraction element and an optical filter stacked with the diffraction element. The optical filter is configured to forwardly deflect a light from a real-world environment incident onto the optical filter, at an incidence angle greater than or equal to a predetermined angle, toward the diffraction element. The diffraction element is configured to substantially transmit the light forwardly deflected by the optical filter.
    Type: Application
    Filed: July 15, 2022
    Publication date: March 16, 2023
    Inventors: Xiayu FENG, Yun-Han LEE, Babak AMIRSOLAIMANI, Mengfei WANG, Junren WANG, Lu LU
  • Publication number: 20230055629
    Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 23, 2023
    Inventors: RAVI VENUGOPALAN, SANDEEP KUMAR GOEL, YUN-HAN LEE
  • Patent number: 11585831
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Publication number: 20230045957
    Abstract: An illuminator usable for illuminating a display panel is disclosed. The illuminator uses a pupil-replicating waveguide to expand a pair of light beams propagating in the waveguide. The light beams may be coupled at a same edge and/or at opposite edges of the waveguide, and are configured to fill each other's dark spots between out-coupled beam portions of the light beams. To improve the illumination uniformity, the two light beams may be orthogonally polarized, and the out-coupling grating strength may be spatially varied along the waveguide.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Fenglin Peng, Ying Geng, Lu Lu, Yun-Han Lee, Jacques Gollier
  • Patent number: 11568119
    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.
    Type: Grant
    Filed: January 17, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
  • Patent number: 11567332
    Abstract: A device includes a light guide. The device also includes a first in-coupling element configured to couple a first input light into the light guide, and a first out-coupling element configured to couple the first input light out of the light guide as a first output light having a first output field of view (“FOV”). The device also includes a second in-coupling element configured to couple a second input light into the light guide. The device further includes a second out-coupling element configured to couple the second input light out of the light guide as a second output light having a second output FOV substantially non-overlapping with the first output FOV. A combination of the first and second output FOVs is larger than at least one of the first or second output FOV, and the first and second input lights have orthogonal polarizations.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: January 31, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Scott Charles Mceldowney, Babak Amirsolaimani, Yun-Han Lee, Lu Lu, Mengfei Wang, Junren Wang
  • Publication number: 20230021670
    Abstract: An illuminator for a display panel includes a light source for providing a light beam and a lightguide coupled to the light source for receiving and propagating the light beam along the substrate. The lightguide includes an array of out-coupling gratings that runs parallel to the array of pixels for out-coupling portions of the light beam from the lightguide such that the out-coupled light beam portions propagate through the substrate and produce an array of optical power density peaks at the array of pixels due to Talbot effect. A period of the array of peaks is an integer multiple of a pitch of the array of pixels.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Inventors: Jacques Gollier, Fenglin Peng, Alexander Koshelev, Giuseppe Calafiore, Lu Lu, Ying Geng, Yun-Han Lee
  • Patent number: 11562946
    Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 24, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yun-Han Lee, Lee-Chung Lu
  • Patent number: 11549984
    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
  • Publication number: 20230003790
    Abstract: A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.
    Type: Application
    Filed: August 3, 2021
    Publication date: January 5, 2023
    Inventors: Ankita PATIDAR, Sandeep Kumar GOEL, Yun-Han LEE
  • Publication number: 20220413205
    Abstract: A device includes a display configured to generate an image light. The device also includes a waveguide optically coupled with the display and configured to guide the image light to an exit pupil of the device. The waveguide includes a grating including a birefringent material, and a birefringence of the grating is configured to increase along a pupil-expanding direction of the device.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 29, 2022
    Inventors: Yun-Han LEE, Lu LU, Mengfei WANG, Fenglin PENG, Junren WANG, Oleg YAROSHCHUK, Yingfei JIANG, Babak AMIRSOLAIMANI, Scott Charles MCELDOWNEY