Patents by Inventor Yun-Han Lee

Yun-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200004913
    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.
    Type: Application
    Filed: October 29, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Vinay KOTHA, Ankita PATIDAR
  • Publication number: 20190332161
    Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a pre-determined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yuan TING, Shereef SHEHATA, Tze-Chiang HUANG, Sandeep Kumar GOEL, Mei WONG, Yun-Han LEE
  • Patent number: 10440281
    Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Ashok Mehta
  • Patent number: 10430334
    Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Publication number: 20190285939
    Abstract: An optical display system includes an information display (image-generating) component, a polarization rotator, a polarization dependent optical element, an input holographic coupler, a light guide and an output holographic coupler. By controlling the polarization of the displayed light through the polarization rotator, the polarization dependent optical element changes the viewable content to different distances from the viewer. This enables the generation of a proper light field which will then be coupled into the light guide through the input holographic coupler, and finally go through the output holographic coupler to a user's eye.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Yun-han Lee, Fenglin Peng, Guanjun Tan, Yishi Weng, Shin-Tson Wu
  • Publication number: 20190229737
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Sandeep Kumar GOEL, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10345883
    Abstract: A power state transformer, a system and a method thereof are disclosed. The power state transformer is coupled with a processing unit model. The power state transformer is configured for counting performance activities executed in the processing unit model, and further for determining a power state of the processing unit model according to count values of the performance activities.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yuan Ting, Shereef Shehata, Tze-Chiang Huang, Sandeep Kumar Goel, Mei Wong, Yun-Han Lee
  • Publication number: 20190123019
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 10268793
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Wu-An Kuo
  • Patent number: 10267857
    Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar Goel, Abhishek Koneru, Tri Ngo, Yun-Han Lee
  • Publication number: 20190113573
    Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.
    Type: Application
    Filed: September 12, 2018
    Publication date: April 18, 2019
    Inventors: SANDEEP KUMAR GOEL, YUN-HAN LEE, ANKITA PATIDAR
  • Publication number: 20190108302
    Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
  • Publication number: 20190109046
    Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 10256828
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Publication number: 20190094303
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 28, 2019
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20190034566
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Application
    Filed: August 31, 2017
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan TING, Sandeep Kumar GOEL, Yun-Han LEE, Mei WONG, Hsin-Cheng CHEN
  • Patent number: 10162925
    Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
  • Patent number: 10163851
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 10163708
    Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 10156607
    Abstract: A bi-directional scan chain includes a plurality of cell structures, each cell structure having a storage device and at least one multiplexer, the plurality of cell structures coupled to one another in a series configuration, wherein an output of a (K?1)-th cell structure is provided as input to the K-th cell structure to provide a forward data shifting operation, and an output of the K-th cell structure is provided as an input to the (K?1)-th cell structure to provide a backward data shifting operation, where K is an integer greater than 1.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee