Abstract: A foil peeling apparatus adapted to a substrate having a foil thereon includes a foil peeling member, a connector and a controller. The foil peeling member has a foil peeling surface. The controller controls the connector to drive the peeling member to move along a path. The foil peeling surface of the peeling member in contact with, with an initial angle, the substrate, feeds toward the substrate for a first displacement, and then moves upwards and toward the substrate when the first feeding angle is decreased.

Abstract: A film-peeling apparatus is adapted to peel a protective film on a surface of a substrate. The surface of the substrate has a bare area which is not covered by the protective film. The film-peeling apparatus includes a punching member, a connector connected to the punching member, and a controller. The controller is configured for driving, through the connector, the punching member to punch at predetermined positions nearby or on a first edge of the protective film adjacent to the bare area.

Abstract: A pixel array substrate includes a substrate, first signal lines, second signal lines, active elements, pixel electrodes, selection lines, a driving unit, and metal lines. Each selection line is intersected with the first signal lines to form a first intersection and second intersections. Each selection line is electrically connected to the first signal line at the first intersection and electrically insulated to the first signal lines at the second intersections. Each selection line has a first portion and a second portion. The first portion is overlapped with the first signal line at the first intersection and separated from the second portion by a gap. The driving unit is electrically connected to the second signal lines and the first portions of the selection lines. Each metal line is overlapped with one of the gaps.

Abstract: Disclosed herein is a method of coating a catalyst support, in which a monolithic catalyst support provided therein with a plurality of longitudinally formed channels is quantitatively coated with catalyst slurry applied to post-treatment of exhaust gas, including the steps of: introducing catalyst slurry into a quantitative container whose bottom is vertically moved; moving a catalyst support to the top of a container such that the bottom of the catalyst support and top of the container are horizontally disposed each other; sealing the bottom of the catalyst support and the top of the container from the outside; moving the bottom of the container upward; and applying a vacuum to the channels of the catalyst support.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.

Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.

Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.

Abstract: Provided is a device for measuring wafer defects, which prevents damage of a wafer and also measures defects at upper, lower and side surfaces of the wafer simultaneously. The device for measuring wafer defects includes a lower blower configured to inject air to a lower surface of a wafer to float the wafer; an upper blower provided to be moved up and down with respect to the lower blower and configured to inject the air to an upper surface of the wafer to fix the wafer; an upper contamination measuring part provided at an upper side of the upper blower and configured to detect contamination on the upper surface of the wafer; a lower contamination measuring part provided at a lower side of the lower blower and configured to detect contamination on the lower surface of the wafer; and a side contamination measuring part provided between the upper and lower blowers and configured to detect contamination on a side surface of the wafer.

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Abstract: The present disclosure relates to liquid enzyme formulations containing one or more alpha-amylases for use in starch processing, wherein the pH of the enzyme formulation is about pH 6.0-8.0, and methods of use thereof. The present disclosure further relates to methods of making a liquid enzyme formulation containing one or more alpha-amylase having improved stability, comprising titrating the pH of the liquid enzyme formulation to a range of pH 6.0-8.0.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

Abstract: An implanting device is used for implanting a membrane in a biological tissue. The implanting device includes a sleeve, a membrane storage element, an injection element and a bubble generating element. The membrane storage element is fixed at the sleeve. The injection element is inserted in the sleeve and the membrane storage element, and includes a capturing end and connecting end. The capturing end is for capturing the membrane and has a hole. The bubble generating element is connected to the connecting end, and is for providing a gas that is then outputted via the hole. By the rotation of the injection element, the capturing end extends straight out of the membrane storage element or retracts straight into the membrane storage element.

Abstract: Disclosed herein is a method of coating a catalyst support, in which a monolithic catalyst support provided therein with a plurality of longitudinally formed channels is quantitatively coated with catalyst slurry applied to post-treatment of exhaust gas, including the steps of: introducing catalyst slurry into a quantitative container whose bottom is vertically moved; moving a catalyst support to the top of a container such that the bottom of the catalyst support and top of the container are horizontally disposed each other; sealing the bottom of the catalyst support and the top of the container from the outside; moving the bottom of the container upward; and applying a vacuum to the channels of the catalyst support.

Abstract: Provided are a reciprocal distribution calculating method and a reciprocal distribution calculating system for cost accounting, in which, when performing cost accounting using a computer, a reciprocal distribution method is used to effectively perform cost accounting of each department. In the reciprocal distribution calculating method and the reciprocal distribution calculating system for cost accounting, reciprocal distribution costs are calculated using the limit and convergence of a transition probability matrix. And, a reciprocal distribution calculation is performed in a completely different way from the method of calculating reciprocal distribution known for the last several tens of years and in an effective manner, thereby calculation of reciprocal distribution costs at a high speed.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Abstract: A touch sensor includes a base layer, first touch sensor columns, second touch sensor columns, and sensing lines. The base layer includes a sensing region and a non-sensing region. The first touch sensor columns extend in a first direction. The first touch sensor columns include first touch electrodes. The first touch electrodes include sub-touch electrodes in the sensing region. The second touch sensor columns include second touch electrodes in the sensing region. The second touch sensor columns are alternately arranged with the first touch sensor columns. The sensing lines are in the non-sensing region. The sensing lines include: first sensing lines electrically connected to the sub-touch electrodes, and second sensing lines electrically connected to the second touch electrodes. The sub-touch electrodes and the second touch electrodes have different widths.

Abstract: An input sensing unit includes sensing electrodes. Each of the sensing electrodes includes: first electrodes arranged in a column extending in a first direction; a second electrode extending in the first direction; first sensing lines connected to the first electrodes, the first sensing lines extending in the first direction; and a second sensing line connected to the second electrode, the second sensing line extending in the first direction. The first sensing lines are connected to first pad portions. The second sensing line is connected to a second pad portion. The second pad portions or some of the first pad portions are disposed between a first pad portion among the first pad portions and the second pad portion, the first pad portion being connected to a first sensing line closest to the second sensing line among the first sensing lines.