Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.

Abstract: A method for forming a FinFET device structure and method for forming the same is provided. The method includes forming an isolation structure over a substrate and forming a first dielectric layer over the isolation structure. The method includes forming a gate structure in the first dielectric layer and forming a deep trench through the first dielectric layer and the isolation structure. The method also includes forming an S/D trench in the first dielectric layer and filling a metal material in the deep trench and the S/D trench to form a deep contact structure and the S/D contact structure. A bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

Abstract: The present application provides a vector denoising method and a vector denoising device for multicomponent seismic data, which relate to the field of seismic data processing technologies. The vector denoising method for multicomponent seismic data includes: decomposing multicomponent seismic gather data to obtain a plurality of small multicomponent seismic data; obtaining quaternary frequency domain seismic data by performing a quaternary Fourier transformation according to each of the plurality of small multicomponent seismic data; extracting frequency slices from the quaternary frequency domain seismic data in a quaternary frequency domain, and filtering the frequency slices by using a Cadzow filtering method to obtain filtered quaternary frequency domain seismic data; and performing an inverse quaternary Fourier transformation on the filtered quaternary frequency domain seismic data to obtain filtered seismic data of each component.

Abstract: A method and system for product knowledge fusion are discloses. The method includes following steps: acquiring original data of a product; performing knowledge extraction on the original data of the product to obtain entities, attributes and semantic relationships related to the product; building an entity information knowledge base according to the entities, attributes and semantic relationships related to the products; fusing the semantic relationships and attributes with the entities and matching the entities by adopting a text matching model to obtain original data of the product corresponding to matched entity information; and establishing a knowledge graph of the product according to the matched entity information. The method and system standardize multi-source heterogeneous data with a knowledge fusion method, thus effectively reducing polysemy and unclear references of knowledge caused by different data structures and sources.

Abstract: A face image straight line processing method, a terminal device, and a storage medium are provided. The method includes: detecting faces and straight lines in an image; determining attributes of each of straight lines based on positions of face frames, and start coordinates and end coordinates of the straight lines; extracting an effective line set from the straight lines; and keeping, during performing face distortion correction on the image, relative positions of points on effective lines in the effective line set unchanged.

Abstract: A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.

Abstract: An accumulator, including a housing and a cover body, one end of the housing being open; the housing is internally provided with an accommodating cavity, the accommodating cavity being internally provided with a filter; a peripheral wall of the housing comprises a first thick wall part, the first thick wall part being provided with an inlet channel, and one end of the inlet channel communicating with the accommodating cavity, while the other end of the inlet channel communicates with the outside; one end of an outlet channel communicates with the accommodating cavity by means of the filter, while the other end of the outlet channel communicates with an outer portion of the housing. The accumulator may be directly welded and fixed to a heat exchange core without requiring a pipeline connection, the risk of external leakage being small, and the anti-seismic performance being high.

Abstract: A processes for solubilization or hydrolysis of a municipal solid waste with an Enzyme composition, comprising: (i) a cellulolytic enzyme composition, and (ii) a protease selected from the group consisting of: (a) a protease having at least 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 100% identity to amino acids 1 to 177 of SEQ ID NO: 1 or a fragment thereof having protease activity; (b) a protease having at least 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 100% identity to SEQ ID NO: 5; (c) a protease having at least 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 100% identity to SEQ ID NO: 32 or a variant thereof; (d) a protease having at least 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 100% identity to SEQ ID NO: 33; and (e) a protease having at least 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 100% identity to amino acids 199 to 564 of SEQ ID NO: 36.

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

Abstract: The present disclosure provides a method for correcting face distortion, an apparatus for correcting face distortion, an electronic device, and a storage medium. The method includes: performing face detection on an obtained image to determine a position of each face box included in the image; determining whether each face box is within a predetermined field of view range based on the position of the face box; and performing distortion correction on a face in a first face box in response to at least a part of the first face box being not within the predetermined field of view range, to generate a corrected image.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.