Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

Abstract: A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

Abstract: An electrical system having a plurality of power converters each having an input in electrical communication with a power source and an output in electrical communication with a load. A controller is configured to receive an output power request for the plurality of power converters. The controller can then select at least one power converter of the plurality of power converters to satisfy the output power request based on an efficiency of power conversion of each of the plurality of power converters and an operating lifespan of each of the plurality of power converters and direct the at least one power converter to produce power to satisfy the output power request.

Abstract: Disclosed is a composition containing 2?-FL for ameliorating, preventing or treating diseases caused by reduction of dopamine. 2?-FL has an advantage of effectively preventing or treating diseases caused by a decrease in dopamine by effectively suppressing degeneration of dopaminergic neurons. In particular, the composition of the present invention is effective in preventing, treating, or ameliorating Parkinson's disease caused by reduction of dopamine because it contains 2?-fucosyllactose (2?-FL) as an active ingredient, thereby suppressing the decrease in dopaminergic neurons and exhibiting an effect of improving motor activity.

Abstract: The present invention provides a spray gun for conveniently adding liquid, including a gun body, a material pot, a thimble assembly and a trigger assembly, the gun body is provided with a liquid filling channel, the lower end of the liquid filling channel communicates with the material pot, and the liquid filling channel penetrates upwardly through the gun body, so that the upper end of the liquid filling channel is connected to the outside world, and the upper end of the gun body is provided with a sealing cover assembly for sealing off the liquid filling channel. The solution, the sealing cover assembly is located on the top of the gun body, and the space for operation is large when liquid is added, so as to realize the purpose of conveniently and quickly adding liquid.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: A fluid control assembly and a fluid control device are provided. The fluid control assembly is provided with an accommodation chamber and a communication port, the communication port being adjacent to the accommodation chamber. The fluid control assembly comprises a connector, a valve core and a sealing member. The connector comprises a side wall portion, the side wall portion forming at least part of the peripheral wall of the accommodation chamber; at least part of the valve core is positioned in the accommodation chamber. The sealing member comprises a sealing body portion, the sealing body portion being clamped between the side wall portion and the valve core. The sealing member comprises pore channels correspondingly communicating with the communication port.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: The photoelectric sensor includes a housing, a light-emitting module, a light-receiving module, and two adhesive members. The housing includes a first upright portion, a second upright portion, and a base. The first upright portion and the second upright portion are connected to the base, the first upright portion has a first concave structure and a first opening, and the second upright portion has a second concave structure and a second opening. The light-emitting module includes a first circuit board and a light-emitting element and is embedded in the first concave structure. The light-emitting element corresponds to the first opening. The light-receiving module includes a second circuit board and a light-receiving element and is embedded in the second concave structure. The light-receiving element corresponds to the second opening. The two adhesive members are respectively provided on side walls of the first concave structure and the second concave structure.

Abstract: A fluid control assembly and a fluid control apparatus are provided. The fluid control assembly comprises a connector, a valve core, and a communication port. The communication port at least comprises a first port, a second port, a third port, a fourth port, and a fifth port. The fluid control assembly has at least one of the four working modes.

Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

Abstract: A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Abstract: A computer-implemented method, computer program product and computer system to automatically perform file management operations is provided. A processor identifies a plurality of files to monitor. A processor generates tracking attributes for the plurality of files. A processor monitors user interactions with the plurality of files. A processor generates prediction vectors for a plurality of file interactions based on the user interactions with the plurality of files. A processor determines at least one file in the plurality of files with tracking attributes that correlate with at least one prediction vector. A processor performs an operation on the at least one file that corresponds with the at least one prediction vector.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall of the gate structure. The FinFET device structure includes a gate contact structure formed over the gate structure, and a first isolation layer surrounding the gate contact structure. A bottom surface of the first isolation layer is lower than a top surface of the gate spacer layer.

Abstract: An image correction method, a terminal device and a non-transitory computer readable storage medium are provided. The method includes: extracting human face attributes of an image; acquiring, from target regions, a first region having a human face correction attribute; acquiring, from the target regions, a second region having a human face protection attribute; and performing image correction on the human face in the first region, and performing pixel compensation, according to background pixels of the image, on a blank region generated by the image correction in the first region.

Abstract: A system in a vehicle includes a controller to implement a neural network to provide current commands based on inputs. The inputs include a torque input. The system also includes a current controller to provide a three-phase voltage through an inverter based on the current commands from the controller. An electric traction motor provides drive power to a transmission of the vehicle based on injection of the three-phase voltage. The current commands resulting from implementation of the neural network are corrected based on estimated torque resulting from the injection of the three-phase voltage to the electric traction motor.

Abstract: A Thevenin equivalent model of a lithium-ion battery cell provides the basis for a simplified cell diagnostic relying on cell current and cell terminal voltage measurements.