Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

Abstract: The present disclosure provides a prestack separating method for a seismic wave, including: receiving P-wave, S1-wave and S2-wave of the seismic wave, wherein the P-wave, S1-wave and S2-wave are reflected from different points; projecting the P-wave, S1-wave and S2-wave into a Z-R-T coordinate system, so as to generate a projection matrix, wherein Z is a vertical component, R is a component of a source-to-receiver azimuth and T is a component orthogonal to the R component; forming vectors of the P-wave, S1-wave and S2-wave as a composite vector; transforming the composite vector to an anisotropic wave vector matrix according to base vectors on the vector directions of the P-wave, S1-wave and S2-wave; and performing a rotation transformation of an affine coordinate system on the anisotropic wave vector matrix to generate a wave separation matrix, thereby solving a problem of error prediction result of fracture parameters caused by the “mode leakage” phenomenon.

Abstract: System and method of dynamically balancing a rechargeable energy storage assembly having two or more respective units, a respective switch for each of the respective units and at least one sensor. The system includes a controller configured to control operation of the respective switch. The respective switch is configured to enable a respective circuit connection to the respective units when in an ON state and disable the respective circuit connection when in an OFF state. The respective units are characterized by a respective state of charge obtained based in part on the at least one sensor. A controller is configured to selectively employ at least one of a plurality of charging modes to charge one or more of the respective units, through operation of the respective switch. The plurality of charging modes includes a rest charging mode, a rapid initial charging mode and a rapid final charging mode.

Abstract: A brain tumor image segmentation method and device are disclosed. The disclosed method includes acquiring a basic white matter template generated based on brain magnetic resonance images of a plurality of healthy samples, collecting corresponding low, mid and high b-value diffusion weighted images of the brain of a patient, segmenting out a tumor region including the tumor body and the edema on each image based on the signal distribution of each image in a first set image group of the patient, removing the normal white matter region from the tumor region according to the basic white matter template and the high b-value diffusion weighted image, and classifying the value of the voxel in each image in a second set image group and a second apparent diffusion coefficient image obtained through calculations to obtain a tumor body region and an edema region.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Described herein is a method for resource aggregation (many-to-one virtualization), comprising: virtualizing CPU by QEMU in a distributed way; organizing a plurality of memories scattered over different machines as pages to providing consistent memory view for guest OS; and performing time synchronization between different machines.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: An electronic device may have a flexible display such as an organic light-emitting diode display. A strain sensing resistor may be formed on a bent tail portion of the flexible display to gather strain measurements. Resistance measurement circuitry in a display driver integrated circuit may make resistance measurements on the strain sensing resistor and a temperature compensation resistor to measure strain. A crack detection line may be formed from an elongated pair of traces that are coupled at their ends to form a loop. The crack detection line may run along a peripheral edge of the flexible display. Crack detection circuitry may monitor the resistance of the crack detection line to detect cracks. The crack detection circuitry may include switches that adjust the length of the crack detection line and thereby allow resistances to be measured for different segments of the line.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

Abstract: An exhaust aftertreatment system for an internal combustion engine includes a selective catalytic reduction (SCR) device, an injection system disposed to inject reductant into the exhaust pipe upstream of the SCR device. A single ammonia sensor is disposed to monitor an exhaust gas feedstream downstream of the SCR device. A controller is in communication with the single ammonia sensor and the internal combustion engine and operatively is connected to the injection system. The controller includes an instruction set that is executable to monitor, via the single ammonia sensor, a magnitude of ammonia in the exhaust gas feedstream downstream of the SCR device and determine NOx efficiency of the SCR device based upon the magnitude of ammonia in the exhaust gas feedstream downstream of the SCR device. A fault is detected in the SCR device based upon the NOx efficiency.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A single chip for generating multiple differential signals and loop-through signals according to a single-ended RF signal inputted to the single chip, wherein delays between different channels of the multiple differential signals and loop-through signals can be minimized for supporting picture-in-picture applications; in addition, the single chip can integrate a power detector and an AGC circuit for controlling the gain of an LNA inside the single chip, and the gain of the LNA can be outputted from the single chip for different usages.

Abstract: The disclosure involves multi-source data assimilation. According to an embodiment, first data associated with an indication of environmental quality in a first region is obtained, and second data associated with an indication of environmental quality in a second region is obtained. The first data is of a higher quality than the second data according to a predetermined criterion. The second data is calibrated according to a relationship between the first and second data in an overlap of the first and second regions. Third data associated with an indication of environmental quality in a third region is determined based on the first data and the calibrated second data, wherein the third region comprises at least the first and second regions.

Abstract: The present disclosure provides a method for controlling an exoskeleton robot. The method comprises checking that a first signal is triggered by a first button, checking a tilt angle after the first signal is triggered, setting an action based on the tilt angle, and executing the action to move the exoskeleton robot. The first signal indicates to change the exoskeleton robot from a standing posture to another posture, and the tilt angle is a leaning-forward angle of a waist assembly of the exoskeleton robot relative to a line vertical to ground. The method utilizes the tilt angle to judge the intent of the user, and thus can simplify the controlling buttons to one or two buttons. Further, the controlling method also monitors the tilt angle to choose a suitable action.