Patents by Inventor Yun Wang

Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210088915
    Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
  • Patent number: 10954838
    Abstract: An emissions control system for a motor vehicle that includes an internal combustion engine includes a first selective catalytic reduction (SCR) device and a reductant injector, The system further includes a model-based controller that is configured to calculate a target amount of reductant to inject to maintain a predetermined ratio between an amount of NH3 and an amount of NOx at the outlet of the first SCR device, and to send a command for receipt by the reductant injector to inject the calculated amount of reductant. The model-based controller is further configured to send a command for receipt by an engine controller to influence NOx production by the engine by modifying an engine operating parameter, based on a calculated target amount of NOx at the inlet of the first SCR device.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 23, 2021
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Yue-Yun Wang, Giuseppe Mazzara Bologna, Vincenzo Alfieri
  • Patent number: 10957604
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
  • Publication number: 20210082349
    Abstract: An electronic device comprises a controller. The controller is configured to provide a first signal to a display of the electronic device to turn off the display. The controller is also configured to provide a second signal to the display to alter a gate source voltage of a drive transistor coupled to a light emitting diode (LED) of a pixel of the display while the display is turned off.
    Type: Application
    Filed: March 27, 2018
    Publication date: March 18, 2021
    Inventors: Junhua Tan, Kingsuk Brahma, Jie Won Ryu, Shengkui Gao, Shiping Shen, Majid Gharghi, Hyunwoo Nho, Injae Hwang, Kavinaath Murugan, Sun-II Chang, Chin-Wei Lin, Hyunsoo Kim, Rui Zhang, Jesse Aaron Richmond, Yun Wang, Hung Sheng Lin
  • Publication number: 20210082925
    Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu
  • Publication number: 20210083114
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Publication number: 20210080613
    Abstract: A method and device for filling invalid regions of terrain elevation model data are provided by the present disclosure. The filling method includes obtaining an isolated invalid grid in first terrain elevation model data, the invalid grid being a grid without a valid elevation value; interpolating an elevation value of the isolated invalid grid by using elevation values of valid grids around the isolated invalid grid, to obtain data-interpolated first terrain elevation model data; obtaining invalid patches in the data-interpolated first terrain elevation model data, each of the invalid patches being a region consisting of at least two adjacent invalid grids; and interpolating elevation values of the invalid grids in the invalid patches by using a further terrain elevation model data other than the first terrain elevation model data, to fill the invalid regions of the first terrain elevation model data.
    Type: Application
    Filed: January 22, 2018
    Publication date: March 18, 2021
    Applicant: XINJIANG GOLDWIND SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Qiankun WANG, Yun WANG, Dongxu LEI
  • Patent number: 10950182
    Abstract: The present disclosure relates generally to systems and methods that may reduce a reduction in visual artifacts related to hysteresis of a light emitting diode (LED) electronic display. In one example, an electronic device may include a controller. The controller is may provide a signal to a pixel of a display of the electronic device while at least a portion of the display is turned off. The signal may include a first current and a second current. The first current may be designed to increase an ambient temperature corresponding to the pixel. The second current may be generated as part of an active panel conditioning operation. By applying the first current and the second current, hysteresis settling times from the pixel may improve, therefore improving speeds of sensing and compensation operations of the electronic device.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Apple Inc.
    Inventors: Junhua Tan, Kingsuk Brahma, Jie Won Ryu, Shengkui Gao, Shiping Shen, Majid Gharghi, Hyunwoo Nho, Injae Hwang, Kavinaath Murugan, Sun-Il Chang, Chin-Wei Lin, Hyunsoo Kim, Rui Zhang, Jesse Aaron Richmond, Yun Wang, Hung Sheng Lin, Alex H. Pai, Chaohao Wang, Wei H. Yao
  • Patent number: 10945916
    Abstract: A foot spa includes a body and an electrolysis device. The body has a receiving space for containing water. The electrolysis device is mounted on a bottom of the body and includes a case, a control module and two electrolyte plates. The control module is mounted inside the body. The two electrolyte plates are mounted on a top portion of the case and are electrically connected to the control module. When the foot spa is operated, salt water is added to the receiving space for the two electrolyte plates to be soaked into the salt water in generation of an electrolytic reaction, such that sodium hydroxide and hypochlorous acid can be generated from the salt water to sterilize and deodorize the feet of users and provide the hygienic advantage.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 16, 2021
    Inventor: Mei-Yun Wang
  • Patent number: 10950728
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Huai Chang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10949415
    Abstract: A computer program product, including: a computer readable storage device to store a computer readable program, wherein the computer readable program, when executed by a processor within a computer, causes the computer to perform operations for logging. The operations include: receiving a transaction including data and a log record corresponding to the data; writing the data to a data storage device; and writing the log record to a log space on a persistent memory device coupled to the data storage device.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ru Fang, Bin He, Hui-I Hsiao, Chandrasekaran Mohan, Yun Wang
  • Publication number: 20210073044
    Abstract: Techniques for warm cloning of computing nodes are provided. A request to clone a first computing node is received. Upon determining that a first transaction of a plurality of transactions is ongoing, a first moment in time when data associated with the first transaction was coherent on the first computing node is identified. Tracking data related to the first transaction is collected, beginning at the first moment in time. Further, a first storage associated with the first computing node is copied to a second storage associated with a second computing node, where the first transaction continues during the copying. The tracking data related to the first transaction is then transmitted to the second computing node.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Mark J. ANDERSON, Thomas P. GIORDANO, Scott D. HELT, David JONES, Curtis D. SCHEMMEL, Shauna ROLLINGS, Yun WANG, Jennifer A. DERVIN, Kristopher C. WHITNEY
  • Patent number: 10943983
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hung Tsai, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 10943818
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10930564
    Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Patent number: 10929241
    Abstract: A method and system for providing file level restore (FLR) service for restoring one or more files stored in a plurality of file systems in a backup of a first virtual machine is provided. The method creates a FLR session for a user, including: creating a virtual disk file in a second virtual machine providing the FLR service, the virtual disk file including an empty file system being mounted as a root folder of a virtual appliance in the second virtual machine; creating a respective folder for each of the plurality of file systems under the root folder; mounting each of the plurality of file systems to the respective folder; and mounting the root folder to a folder of the second virtual machine. The method restores the one or more files by the user through accessing the folder of the second virtual machine in the FLR session.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jing Yu, Ming Zhang, Boda Lei, Yun Wang, Liang Zheng
  • Publication number: 20210050385
    Abstract: An electronic device includes a stack, and the stack includes a substrate, and a multi-layer structure deposited on the substrate and including a set of TFTs. The electronic device further includes a photodetector attached to the multi-layer structure and including an organic photosensitive material. The organic photosensitive material is electrically connected to a TFT in the set of TFTs. Another electronic device includes a stack, and the stack includes a substrate, and a multi-layer structure deposited on the substrate. The multi-layer structure includes a first set of layers including a set of TFTs, and a second set of layers including a PIN diode. The PIN diode is configured to operate as a photodetector and receive at least one wavelength of electromagnetic radiation, and is electrically connected to a TFT in the set of TFTs.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 18, 2021
    Inventors: Ching-Sang Chuang, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Ting-Kuo Chang, Yun Wang
  • Publication number: 20210050268
    Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Yun Lee, Chung-Ting Ko, Chen-Ming Lee, Mei-Yun Wang, Fu-Kai Yang
  • Patent number: 10922906
    Abstract: A system for monitoring operation of a vehicle includes a processing device including an interface configured to receive measurement data from sensing devices configured to measure parameters of a vehicle system. The processing device is configured to receive measurement data from each of the plurality of sensing devices, and in response to detection of a malfunction in the vehicle, input at least a subset of the measurement data to a machine learning classifier associated with a vehicle subsystem, the classifier configured to define a class associated with normal operation of the vehicle subsystem. The processing device is also configured to determine whether the subset of the measurement data belongs to the class, and based on at least a selected amount of the subset of the measurement data being outside of the class, output a fault indication, the fault indication identifying the vehicle subsystem as having a contribution to the malfunction.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 16, 2021
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Yue-Yun Wang, Ibrahim Haskara, David Sun, Yusheng Zou, Shiming Duan, Chi-kuan Kao, Xiangxing Lu
  • Patent number: D911315
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 23, 2021
    Assignee: RHA Technologies Limited
    Inventors: Kyle Hutchison, Jo-Yun Wang, Sam Prentice, David Keating, Heather Rebecca Guyan