Patents by Inventor Yun Yue

Yun Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180059531
    Abstract: The present disclosure provides a phase shift mask. The phase shift mask includes a transparent substrate; an etch stop layer disposed on the substrate; and a tunable transparent material layer disposed on the etch stop layer and patterned to have an opening, wherein the tunable transparent material layer is designed to provide phase shift and has a transmittance greater than 90%.
    Type: Application
    Filed: May 17, 2017
    Publication date: March 1, 2018
    Inventors: Yun-Yue Lin, Hsin-Chang Lee
  • Patent number: 9864270
    Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Shin Ma, Tsiao-Chen Wu, Chi-Ming Yang, Chyi Shyuan Chern, Chih-Cheng Lin, Yun-Yue Lin
  • Publication number: 20170351170
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 7, 2017
    Inventors: AMO CHEN, YUN-YUE LIN, TA-CHENG LIEN, HSIN-CHANG LEE, CHIH-CHENG LIN, JENG-HORNG CHEN
  • Patent number: 9759997
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Amö Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
  • Publication number: 20170205705
    Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Jeng-Shin Ma, Tsiao-Chen Wu, Chi-Ming Yang, Chyi Shyuan Chern, Chih-Cheng Lin, Yun-Yue Lin
  • Publication number: 20170176850
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Amö Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, JENG-HORNG CHEN
  • Patent number: 9651857
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Ta-Cheng Lien, Anthony Yen
  • Publication number: 20160299419
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 13, 2016
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • Patent number: 9366953
    Abstract: The present disclosure provides a lithography mask comprising a substrate, a reflective multiplayer (ML) on the substrate, a barrier layer on the reflective ML, and an absorber layer over the barrier layer. In some embodiments, a thickness of the barrier layer is less than or equal to about 10 nm. In some embodiments, a portion of the absorber layer and a portion of the barrier layer are removed. The present disclosure also provides a method for fabricating a lithography mask, and a method for patterning a substrate using a lithography mask.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • Patent number: 9360749
    Abstract: A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: June 7, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Patent number: 9341937
    Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Patent number: 9287422
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: March 15, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Fang Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Patent number: 9269840
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 23, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Fang Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Publication number: 20150309404
    Abstract: A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yun-Yue LIN, Chia-Jen CHEN, Hsin-Chang LEE, Anthony YEN
  • Publication number: 20150309401
    Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yue LIN, Chia-Jen CHEN, Hsin-Chang LEE, Anthony YEN
  • Publication number: 20150278813
    Abstract: Determining a temporary transaction limit is disclosed, including: receiving a transaction request message, wherein the transaction request message includes a total transaction cost and identifying information associated with a user; determining that the total transaction cost is greater than a predetermined limit; retrieving historical transaction data associated with a plurality of users; determining a plurality of clustered classifications from the historical transaction data associated with the plurality of users; determining a clustered classification from the plurality of clustered classifications based on historical transaction data associated with the user; determining a dynamic quota corresponding to the clustered classification for the user using a predetermined mapping rule; and determining whether the transaction request message is approved based on comparing the total transaction cost to a temporary transaction limit, wherein the temporary transaction limit comprises a combination of the predeter
    Type: Application
    Filed: March 12, 2015
    Publication date: October 1, 2015
    Inventors: Yun Yue, Ji Huang, Zhi Ning
  • Publication number: 20150205194
    Abstract: The present disclosure provides a lithography mask comprising a substrate, a reflective multiplayer (ML) on the substrate, a barrier layer on the reflective ML, and an absorber layer over the barrier layer. In some embodiments, a thickness of the barrier layer is less than or equal to about 10 nm. In some embodiments, a portion of the absorber layer and a portion of the barrier layer are removed. The present disclosure also provides a method for fabricating a lithography mask, and a method for patterning a substrate using a lithography mask.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yue LIN, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • Publication number: 20150177612
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Ta-Cheng Lien, Anthony Yen
  • Patent number: 8974988
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Anthony Yen, Chia-Jen Chen
  • Patent number: 8916482
    Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen