Patents by Inventor Yun Yue

Yun Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STRUCTURE OF PELLICLE-MASK STRUCTURE WITH VENT STRUCTURE
    Publication number: 20190137865
    Abstract: Structures of a pellicle-mask structure are provided. The pellicle-mask structure includes a mask substrate, a pellicle frame over the mask substrate. The pellicle frame includes a side portion with an inside surface and an outside surface opposite to each other. The pellicle-mask structure also includes a vent structure in the side portion and connecting the inside surface and the outside surface, and a pellicle membrane over the pellicle frame. The pellicle-mask structure further includes a pellicle membrane adhesive between the pellicle membrane and the pellicle frame, and a first heat-dissipating filler in the pellicle membrane adhesive.
    Type: Application
    Filed: February 5, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yun-Yue LIN
  • HIGH QUALITY FACTOR FIN METAL OXIDE SEMICONDUCTOR VARACTOR WITH IMPROVED NUMBER OF FINS
    Publication number: 20190115342
    Abstract: A FinMosVar (fin metal oxide semiconductor (MOS) varactor) has an improved number of fins. The number of fins are determined based on a measured or calculated gate resistance of the FinMosVar and a measured or calculated capacitance of the FinMosVar. The number of fins is less than twenty (20) fins. The FinMosVar also includes a source region, a drain region and a channel region. The drain region has a same type of doping as the source region. The channel region has the same type of doping as the source region.
    Type: Application
    Filed: January 4, 2018
    Publication date: April 18, 2019
    Inventors: Ye LU, Yun YUE
  • Transistor with fluorinated graphene spacer
    Patent number: 10263080
    Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Junjing Bao, Bin Yang, Lixin Ge, Yun Yue
  • LITHOGRAPHY MASK AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20190101818
    Abstract: A method of manufacturing a phase shift mask includes forming a doped silicon nitride layer on a mask substrate and forming an opaque layer on the doped silicon nitride layer. The opaque layer and doped silicon nitride layer are then patterned to expose portions of the mask substrate to form a plurality of mask features comprising the opaque layer disposed on the doped silicon nitride layer. Portions of the opaque layer are then removed from some of the mask features.
    Type: Application
    Filed: April 27, 2018
    Publication date: April 4, 2019
    Inventor: Yun-Yue LIN
  • EXTREME ULTRAVIOLET MASK AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190101817
    Abstract: A method of manufacturing an extreme ultraviolet mask, including forming a multilayer Mo/Si stack including alternating Mo and Si layers over a first major surface of a mask substrate, and forming a capping layer over the multilayer Mo/Si stack. An absorber layer is formed on the capping layer, and a hard mask layer is formed over the absorber layer. The hard mask layer is patterned to form a hard mask layer pattern. The hard mask layer pattern is extended into the absorber layer to expose the capping layer and form a mask pattern. A border pattern is formed around the mask pattern. The border pattern is extended through the multilayer Mo/Si stack to expose the mask substrate and form a trench surrounding the mask pattern. A passivation layer is formed along sidewalls of the trench.
    Type: Application
    Filed: April 30, 2018
    Publication date: April 4, 2019
    Inventor: Yun-Yue LIN
  • PELLICLE REMOVAL METHOD
    Publication number: 20190094683
    Abstract: A method of removing a pellicle from a photomask includes removing a portion of a membrane from a pellicle frame, wherein the pellicle frame remains attached to the photomask following the removing of the portion of the membrane. The method further includes removing the pellicle frame from the photomask. The method further includes cleaning the photomask.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 28, 2019
    Inventors: Chue San YOO, Chih-Chiang TU, Chien-Cheng CHEN, Jong-Yuh CHANG, Kun-Lung HSIEH, Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN
  • ENHANCED ACTIVE AND PASSIVE DEVICES FOR RADIO FREQUENCY (RF) PROCESS AND DESIGN TECHNOLOGY
    Publication number: 20190027554
    Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.
    Type: Application
    Filed: November 17, 2017
    Publication date: January 24, 2019
    Inventors: Ye LU, Yun YUE, Phanikumar KONKAPAKA, Bin YANG, Chuan-Hsing CHEN
  • Pellicle fabrication methods and structures thereof
    Patent number: 10162258
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yue Lin, Hsuan-Chen Chen, Chih-Cheng Lin, Hsin-Chang Lee, Yao-Ching Ku, Wei-Jen Lo, Anthony Yen, Chin-Hsiang Lin, Mark Chien
  • SELF-ALIGNED CONTACT (SAC) ON GATE FOR IMPROVING METAL OXIDE SEMICONDUCTOR (MOS) VARACTOR QUALITY FACTOR
    Publication number: 20180366592
    Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 20, 2018
    Inventors: Ye LU, Yun YUE, Chuan-Hsing CHEN, Bin YANG, Lixin GE, Ken LIAO
  • TRANSISTOR WITH FLUORINATED GRAPHENE SPACER
    Publication number: 20180342585
    Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.
    Type: Application
    Filed: August 8, 2017
    Publication date: November 29, 2018
    Inventors: Ye LU, Junjing BAO, Bin YANG, Lixin GE, Yun YUE
  • TRANSISTOR WITH LOW RESISTIVITY CARBON ALLOY
    Publication number: 20180342513
    Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 29, 2018
    Inventors: Ye LU, Junjing BAO, Bin YANG, Lixin GE, Yun YUE
  • PELLICLE AND METHOD OF USING THE SAME
    Publication number: 20180329288
    Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle. The frame further includes a recess in a bottom surface of the frame. The pellicle further includes a membrane extending across the frame. The pellicle further includes a gasket configured to fit within the recess.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 15, 2018
    Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN
  • PELLICLE STRUCTURES AND METHODS OF FABRICATING THEREOF
    Publication number: 20180292744
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN, Hsuan-Chen CHEN, Hsuan-I WANG, Anthony YEN
  • Graphene pellicle for extreme ultraviolet lithography
    Patent number: 10012899
    Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin
  • PELLICLE FABRICATION METHODS AND STRUCTURES THEREOF
    Publication number: 20180173092
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Yun-Yue LIN, Hsuan-Chen CHEN, Chih-Cheng LIN, Hsin-Chang LEE, Yao-Ching KU, Wei-Jen LO, Anthony YEN, Chin-Hsiang LIN, Mark CHIEN
  • PELLICLE STRUCTURES AND METHODS OF FABRICATING THEREOF
    Publication number: 20180173093
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN, Hsuan-Chen CHEN, Hsuan-I WANG, Anthony YEN
  • Pellicle structures and methods of fabricating thereof
    Patent number: 10001701
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Cheng Hsu, Hsin-Chang Lee, Yun-Yue Lin, Hsuan-Chen Chen, Hsuan-I Wang, Anthony Yen
  • Lithography mask
    Patent number: 9995999
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • LITHOGRAPHY MASK WITH BOTH TRANSMISSION-TYPE AND REFLECTIVE-TYPE OVERLAY MARKS AND METHOD OF FABRICATING THE SAME
    Publication number: 20180149959
    Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 31, 2018
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
  • Graphene Pellicle for Extreme Ultraviolet Lithography
    Publication number: 20180059534
    Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
    Type: Application
    Filed: November 18, 2016
    Publication date: March 1, 2018
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin