Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

Abstract: A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4e1017.

Abstract: A mask for extreme ultraviolet (EUV) lithography includes a multilayer (ML) stack including alternating metal and semiconductor layers disposed over a first surface of a mask substrate, a capping layer disposed over the ML stack, and an absorber layer disposed over the capping layer. An image pattern is formed in the absorber layer. A border layer surrounding the image pattern is disposed over the absorber layer.

Abstract: A pellicle for an EUV photo mask includes a first capping layer, a matrix layer disposed over the first capping layer, a second capping layer disposed over the matrix layer; and a metallic layer disposed over the second capping layer.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.

Abstract: A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4 e1017.

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.

Abstract: The present disclosure provides a mask. The mask includes a substrate; an etch stop layer disposed on the substrate, wherein the etch stop layer includes at least one of ruthenium oxide, tungsten nitride, and titanium nitride and is doped with at least one of phosphorous (P), calcium (Ca), and sodium (Na); and a material layer disposed on the etch stop layer and patterned to have an opening, wherein the etch stop layer completely covers a portion of the substrate within the opening.

Abstract: Determining a temporary transaction limit is disclosed, including: receiving a transaction request message, wherein the transaction request message includes a total transaction cost and identifying information associated with a user; determining that the total transaction cost is greater than a predetermined limit; retrieving historical transaction data associated with a plurality of users; determining a plurality of clustered classifications from the historical transaction data associated with the plurality of users; determining a clustered classification from the plurality of clustered classifications based on historical transaction data associated with the user; determining a dynamic quota corresponding to the clustered classification for the user using a predetermined mapping rule; and determining whether the transaction request message is approved based on comparing the total transaction cost to a temporary transaction limit, wherein the temporary transaction limit comprises a combination of the predeter

Abstract: A pellicle for an EUV photo mask includes a base membrane layer, a core layer disposed over the base membrane layer and one or more metallic layers disposed over the core layer.

Abstract: The present disclosure provides a phase shift mask. The phase shift mask includes a transparent substrate; an etch stop layer disposed on the substrate; and a tunable transparent material layer disposed on the etch stop layer and patterned to have an opening, wherein the tunable transparent material layer is designed to provide phase shift and has a transmittance greater than 90%.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

Abstract: A label of a message to be sent is detected as a message label for a non-real-time transmission. For a user device group associated with the message to be sent and based on a timely-response rate and a correction scheme, an optimal time period to respond to a message for each user device in the user device group is dynamically determined. Based on the optimal time period for each user device to respond to a message, the message to be sent is separately sent to a corresponding user device in the user device group.

Abstract: A reticle and a method for manufacturing a reticle are provided. The method includes forming a reflective multilayer (ML) over a front-side surface of a mask substrate. The method further includes forming a capping layer over the reflective ML. The method further includes forming a sacrificial multilayer over the capping layer. The method further includes forming an opening in the sacrificial multilayer to expose the capping layer. The method further includes forming a first absorption layer over the sacrificial multilayer and covering the capping layer in the opening. The method further includes removing the first absorption layer outside the opening in the sacrificial multilayer to form a first absorption pattern on a portion of the capping layer.

Abstract: Structures of a pellicle-mask structure are provided. The pellicle-mask structure includes a mask substrate, a pellicle frame over the mask substrate. The pellicle frame includes a side portion with an inside surface and an outside surface opposite to each other. The pellicle-mask structure also includes a vent structure in the side portion and connecting the inside surface and the outside surface, and a pellicle membrane over the pellicle frame. The pellicle-mask structure further includes a pellicle membrane adhesive between the pellicle membrane and the pellicle frame, and a first heat-dissipating filler in the pellicle membrane adhesive.

Abstract: A FinMosVar (fin metal oxide semiconductor (MOS) varactor) has an improved number of fins. The number of fins are determined based on a measured or calculated gate resistance of the FinMosVar and a measured or calculated capacitance of the FinMosVar. The number of fins is less than twenty (20) fins. The FinMosVar also includes a source region, a drain region and a channel region. The drain region has a same type of doping as the source region. The channel region has the same type of doping as the source region.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.