Patents by Inventor Yun Yue

Yun Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8753788
    Abstract: An apparatus includes a probe tip configured to contact the mask, a cantilever configured to mount the probe tip wherein the cantilever includes a mirror, an optical unit having a light source projecting a light beam on the mirror and a light detector receiving a reflected light beam from the mirror, and an electrical power supply configured to connect the probe tip. The apparatus further includes a computer system configured to connect the optical unit, the electrical power supply, and the stage. The electrical power supply provides an electrical current to the probe tip and heats the probe tip to a predetermined temperature. The heated probe tip repairs a defect by smoothing and reducing a dimension of the defect, and inducing structural deformations of multilayer that cancel out the distortion (of multilayer) caused by buried defects using the heated probe tip as a thermal source canning the defect.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Yu, Yun-Yue Lin
  • Patent number: 8679707
    Abstract: A method of fabricating an extreme ultraviolet (EUV) mask is disclosed. The method includes providing a substrate, forming a reflective multilayer (ML) over the substrate, forming a buffer layer over the reflective ML, forming an absorption layer over the buffer layer and forming a capping layer over the absorption layer. The capping layer and the absorption layer are etched to form the EUV mask.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Pei-Cheng Hsu, Chia-Jen Chen, Ta-Cheng Lien, Anthony Yen
  • Publication number: 20140038088
    Abstract: A method of fabricating an extreme ultraviolet (EUV) mask is disclosed. The method includes providing a substrate, forming a reflective multilayer (ML) over the substrate, forming a buffer layer over the reflective ML, forming an absorption layer over the buffer layer and forming a capping layer over the absorption layer. The capping layer and the absorption layer are etched to form the EUV mask.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY.LTD
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Pei-Cheng Hsu, Chia-Jen Chen, Ta-Cheng Lien, Anthony Yen
  • Publication number: 20130280644
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Anthony Yen, Chia-Jen Chen
  • Publication number: 20130260573
    Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen
  • Publication number: 20130260289
    Abstract: A method of fabricating a lithography mask with carbon-based-charging-dissipation (CBCD) layer is disclosed. The method includes providing a substrate, depositing an opaque layer on the substrate, coating a photoresist and depositing a charging dissipation layer on the photoresist. The photoresist is patterned by an electron-beam writing. The CBCD layer is removed during developing the photoresist.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Ta-Cheng Lien, Anthony Yen
  • Patent number: 8502068
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: August 6, 2013
    Assignee: National Taiwan University
    Inventors: Wei-Fang Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Patent number: 8325522
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Patent number: 8315100
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 20, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Publication number: 20120211070
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 23, 2012
    Applicant: National Taiwan University
    Inventors: WEI-FANG SU, CHUN-WEI CHEN, JIH-JEN WU, YUN-YUE LIN
  • Publication number: 20120214274
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 23, 2012
    Applicant: National Taiwan University
    Inventors: WEI-FANG SU, CHUN-WEI CHEN, JIH-JEN WU, YUN-YUE LIN
  • Publication number: 20120208316
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 16, 2012
    Applicant: National Taiwan University
    Inventors: WEI-FANG SU, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Patent number: 8218370
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 10, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Patent number: 8198531
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: June 12, 2012
    Assignee: National Taiwan University
    Inventors: Wei-Fan Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Publication number: 20110308613
    Abstract: The present invention discloses a photovoltaic device comprising a multilayer structure for generating and transporting charge, wherein the multilayer structure comprises: a substrate; an anode layer; a hole transporting layer; a first nanostructure/conjugated polymer hybrid layer; an network-shaped electron transporting layer matched to the hybrid layer; and a cathode layer. The mentioned electron transporting layer is composed of a plurality of second nanostructures, and the plurality of second nanostructures is staked on each other, so as to form the interconnecting network. Furthermore, this invention also discloses methods for forming the photovoltaic device.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 22, 2011
    Applicant: National Taiwan University
    Inventors: Tsung-Wei Tseng, Wei-Fang Su, Chun-Wei Chen, Yun-Yue Lin
  • Publication number: 20110116318
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Publication number: 20110116324
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Publication number: 20110116319
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Patent number: 7903465
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 8, 2011
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Publication number: 20090038677
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Application
    Filed: April 21, 2008
    Publication date: February 12, 2009
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Fang Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin