Abstract: A pellicle for an EUV photo mask includes a first capping layer, a matrix layer disposed over the first capping layer, a second capping layer disposed over the matrix layer; and a metallic layer disposed over the second capping layer.

Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.

Abstract: A computer-implemented method and system for determining placement of a sensor component on a utility pipe. Data relating to the utility pipe is inputted which is processed to generate one or more variables. One or more models are trained, via the one or more variables, to produce an output indicative of a likelihood of failure variable associated with the utility pipe from each model. The outputs from all models are preferably combined into an ensemble output indicative of a likelihood of failure associated with the utility pipe. A consequence of failure variable associated with the utility pipe is determined preferably utilizing a plurality of weighted variables. A sensor placement determinative variable is then determined contingent upon the ensemble output and the consequence of failure variable associated with the utility pipe.

Abstract: A method of manufacturing an extreme ultraviolet mask, including forming a multilayer Mo/Si stack including alternating Mo and Si layers over a first major surface of a mask substrate, and forming a capping layer over the multilayer Mo/Si stack. An absorber layer is formed on the capping layer, and a hard mask layer is formed over the absorber layer. The hard mask layer is patterned to form a hard mask layer pattern. The hard mask layer pattern is extended into the absorber layer to expose the capping layer and form a mask pattern. A border pattern is formed around the mask pattern. The border pattern is extended through the multilayer Mo/Si stack to expose the mask substrate and form a trench surrounding the mask pattern. A passivation layer is formed along sidewalls of the trench.

Abstract: A label of a message to be sent is detected as a message label for a non-real-time transmission. For a user device group associated with the message to be sent and based on a timely-response rate and a correction scheme, an optimal time period to respond to a message for each user device in the user device group is dynamically determined. Based on the optimal time period for each user device to respond to a message, the message to be sent is separately sent to a corresponding user device in the user device group.

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

Abstract: A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

Abstract: A mask for extreme ultraviolet (EUV) lithography includes a multilayer (ML) stack including alternating metal and semiconductor layers disposed over a first surface of a mask substrate, a capping layer disposed over the ML stack, and an absorber layer disposed over the capping layer. An image pattern is formed in the absorber layer. A border layer surrounding the image pattern is disposed over the absorber layer.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process. The apparatus includes a mask defining a circuit pattern to be transferred. The apparatus further includes a pellicle including a pattern formed in a first surface, wherein the pellicle is attached to the mask at the first surface. The apparatus also includes an adhesive material layer disposed between the mask and the first surface. The pattern may include a plurality of capillaries. Each capillary of the plurality of capillaries may have a dimension in a plane of the first surface between about 1 ?m and about 500 ?m. Each capillary of the plurality of capillaries may have a ratio of depth to width greater than or equal to about 100. The adhesive material layer may include an adhesive having a glass transition temperature (Tg) greater than room temperature.

Abstract: A method of forming a mask includes forming a reflective multilayer over a substrate; forming a capping layer over the reflective multilayer, in which the capping layer includes a ruthenium-containing material and a low carbon solubility material that has a carbon solubility lower than a carbon solubility of the ruthenium-containing material; forming an absorption layer over the capping layer; and etching the absorption layer until exposing the capping layer.

Abstract: A mask for extreme ultraviolet (EUV) lithography includes a multilayer (ML) stack including alternating metal and semiconductor layers disposed over a first surface of a mask substrate, a capping layer disposed over the ML stack, and an absorber layer disposed over the capping layer. An image pattern is formed in the absorber layer. A border layer surrounding the image pattern is disposed over the absorber layer.

Abstract: A label of a message to be sent is detected as a message label for a non-real-time transmission. For a user device group associated with the message to be sent and based on a timely-response rate and a correction scheme, an optimal time period to respond to a message for each user device in the user device group is dynamically determined. Based on the optimal time period for each user device to respond to a message, the message to be sent is separately sent to a corresponding user device in the user device group.

Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle; and a bottom surface of the frame defines only a single recess therein. The pellicle further includes a gasket configured to fit within the single recess.

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Abstract: A pellicle includes a frame. The frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle. The frame further includes a recess in a bottom surface of the frame. The pellicle further includes a membrane extending across the frame. The pellicle further includes a gasket configured to fit within the recess.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

Abstract: A label of a message to be sent is detected as a message label for a non-real-time transmission. For a user device group associated with the message to be sent and based on a timely-response rate and a correction scheme, an optimal time period to respond to a message for each user device in the user device group is dynamically determined. Based on the optimal time period for each user device to respond to a message, the message to be sent is separately sent to a corresponding user device in the user device group.