Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly and a first driving assembly. The movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The optical element driving mechanism further includes a first opening, and an external light beam travels along a first axis to pass through the first opening.

Abstract: A wearable device and a method for performing a registration process in the wearable device are provided. The wearable device includes a light source, a light sensor and a microcontroller that performs the method. In the method, the light source is activated to emit a detection light and the light sensor senses a reflected light. A light intensity of the reflected light is calculated. Specifically, an upper limit and a lower limit are referred to for detecting whether the wearable device is properly worn by a person. For example, since the wearable device can be worn on the person's wrist, the registration value is used to detect whether the wearable device is away from the wrist.

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Abstract: A driving circuit of fluid pump module includes a microprocessor, a primary boost circuit, and a pump driving circuit is provided. The microprocessor receives an output signal with a large-width variable rectangular waveform, a driving voltage, a first detection current-feedback signal, and a second detection current-feedback signal. The primary boost circuit converts an inputted driving voltage into a direct current with a certain high voltage. The pump driving circuit receives the certain high voltage and is connected with the microprocessor to receive the voltage control signal and the pulse-width modulation (PWM) signal. The secondary boost circuit receives the certain high voltage to boost the certain high voltage into a working voltage for the fluid pump. The operation driving circuit receives the working voltage and provides the pulse-width modulation signal for the fluid pump through the second detection current-feedback signal.

Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, trench oxide layers, semiconductor layer structures, a dielectric layer structure and a metal structure. The substrate structure includes a base layer and an epitaxial layer having a plurality of trenches. A trench depth of each trench is X1 micrometer. The doped regions are respectively formed at bottoms of the trenches. The trench oxide layers are respectively formed on inner walls of the trenches. An oxide layer thickness of each trench oxide layer is X2 micrometers. X1 and X2 conform to the following relationship: 0.05X1?X2?0.25X1. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the semiconductor layer structures. The metal structure is formed on the dielectric layer structure.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Abstract: A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.

Abstract: A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.

Abstract: A decoding device for an absolute positioning code is provided. The decoding device includes a linear feedback shift register (LFSR), a lookup table (LUT) circuit, a counter circuit, and a computation circuit. The LFSR includes n registers, for loading the absolute positioning code with a first frequency. The LFSR performs shifting operation according to a clock signal having a second frequency greater than or equal to the first frequency. The LUT circuit outputs a lookup result and a valid flag according to values stored in the n registers. The lookup result has k different data, k?(2n?1). The counter circuit resets according to the valid flag, and performs counting operation according to the clock signal to generate a counting result. The computation circuit performs calculation according to the lookup result and the counting result to generate a decoding result when the valid flag indicates valid.

Abstract: A decoding device for an absolute positioning code is provided. The decoding device includes a linear feedback shift register (LFSR), a lookup table (LUT) circuit, a counter circuit, and a computation circuit. The LFSR includes n registers, for loading the absolute positioning code with a first frequency. The LFSR performs shifting operation according to a clock signal having a second frequency greater than or equal to the first frequency. The LUT circuit outputs a lookup result and a valid flag according to values stored in the n registers. The lookup result has k different data, k?(2n?1). The counter circuit resets according to the valid flag, and performs counting operation according to the clock signal to generate a counting result. The computation circuit performs calculation according to the lookup result and the counting result to generate a decoding result when the valid flag indicates valid.

Abstract: Task flows are utilized for real-time page compositions, real-time flow compositions, or both. At design time, a plurality of task flows are provided as a database or library. A manager, or other type of user, can associate task flows with dynamic regions in an application page being designed. The application page can include one or more dynamic regions that act as a container for task flows. Metadata is generated from the customization of input parameters. At runtime, application pages are generated on-the-fly for display in a user interface. The application pages are composed according to the task flows embedded therein. The application pages are presented to the user according to an application flow. Through a user interface, the user can enter and retrieve information related to governance, risk, and compliance (GRC) activities, or other types of activities.

Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.

Abstract: The invention discloses an electrical sensor for a two-wire power cable. The sensor includes: a flexible substrate joined onto the power cable or the protective jacket thereon; an inductive coil formed on the flexible substrate; a pair of metal electrodes formed on the flexible substrate and at the opposite sides of the power cable, respectively; and a readout circuit formed on the flexible substrate, electrically connected to the inductive coil so as to measure the current in the power cable, and electrically connected to the metal electrodes so as to measure the voltage in the power cable.

Abstract: A method of enhancing 3D image information density, comprising providing a confocal fluorescent microscope and a rotational stage. 3D image samples at different angles are collected. A deconvolution process of the 3D image samples by a processing unit is performed. A registration process of the deconvoluted 3D image samples by the processing unit is performed. An interpolation process of the registered 3D image samples by the processing unit is performed to output a 3D image in high resolution.