Patents by Inventor Yusuke Kobayashi
Yusuke Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10566440Abstract: A method for producing a semiconductor device includes implanting protons from a rear surface of a semiconductor substrate of a first conductivity type, and after the implanting protons, forming a first semiconductor region of the first conductivity type having a impurity concentration higher than that of the semiconductor substrate by performing an annealing process for the semiconductor substrate in an annealing furnace. The forming a first semiconductor region includes substituting oxygen gas for nitrogen gas in a normal pressure atmosphere, thereby reducing a partial pressure of the oxygen in the annealing furnace, and after the subtracting oxygen gas, performing the annealing process in the annealing furnace with a hydrogen gas atmosphere in a range of 300° C. to 450° C. The hydrogen gas atmosphere includes a volume concentration of hydrogen in a range of 6% to 30%.Type: GrantFiled: March 26, 2018Date of Patent: February 18, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Takashi Yoshimura
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Patent number: 10546950Abstract: At bottom of a gate trench, a conductive layer is provided. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and the n-type current spreading region. The Schottky junction constitutes one unit cell of a trench-type SBD. In the gate trench, a gate electrode is provided on the conductive layer, via an insulating layer. The gate electrode constitutes one unit cell of a trench-gate-type vertical MOSFET. In other words, one unit cell of the trench gate MOSFET and one unit cell of the trench-type SBD are disposed built into a single gate trench and oppose each other in a depth direction.Type: GrantFiled: August 27, 2018Date of Patent: January 28, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Shinsuke Harada
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Patent number: 10522673Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.Type: GrantFiled: August 30, 2018Date of Patent: December 31, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
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Patent number: 10507684Abstract: A writing implement is provided which is designed to draw lines using capillary action, wherein the width of the line can be freely adjusted while the line is being drawn and it is possible to draw lines of almost the same width at the beginning of the use of the writing implement as at the end of use. A felt-tip pen 1 is provided with an ink reservoir 11, a collector 17, and a core 29 for drawing by capillary action the ink that has been dispensed by the collector 17, dispensing the drawn ink from the tip, and adhering same to a paper surface. Even in repetitive writing, the rate of variability in the width of the lines drawn at the end of use with respect to the width of lines drawn at the beginning of use is 10% or less.Type: GrantFiled: December 28, 2016Date of Patent: December 17, 2019Assignee: MITSUBISHI PENCIL COMPANY, LIMITEDInventors: Tooru Nakajima, Yusuke Kobayashi, Kensuke Inoue, Kazuhiko Furukawa
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Publication number: 20190375673Abstract: The present invention relates to a vehicle-mounted display device disposed in an interior member of a vehicle. The vehicle-mounted display device of the invention includes: a display panel; a cover glass covering the display panel; a housing accommodating the display panel; and a holding portion holding a position of the housing, in which the cover glass is a tempered glass having a thickness being 0.5 to 2.Type: ApplicationFiled: August 20, 2019Publication date: December 12, 2019Applicant: AGC Inc.Inventors: Kyohei HASHIMOTO, Atsushi INOUE, Yasuhiro INOUE, Yasumasa KATO, Yasuji FUKASAWA, Yusuke KOBAYASHI, Masaaki KONISHI
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Publication number: 20190352227Abstract: A chemically strengthened glass includes a compressive stress layer. A compressive stress is 200 MPa or more at a surface of the chemically strengthened glass. A depth in the compressive stress layer at which the compressive stress is 50 MPa from the surface is 50 ?m or more. A depth in the compressive stress layer at which the compressive stress is 30 MPa from the surface is 60 ?m or more. A critical stress intensity factor KIC is 0.75 MPa·m1/2 or more.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Applicant: AGC Inc.Inventors: Akio Koike, Yusuke Kobayashi
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Patent number: 10483897Abstract: A switched reluctance motor system includes a switched reluctance motor, a rotor including a plurality of salient poles, a stator including a plurality of salient poles, coils of three phases wound around the salient poles of the stator, and an electronic control unit. The electronic control unit is configured to drive the switched reluctance motor in a pole configuration pattern of NSNSNS in which the salient poles of the stator that have different polarities are alternately arranged. The electronic control unit is configured to perform current waveform control when an excitation sound frequency of a given order coincides with a resonance frequency of the switched reluctance motor.Type: GrantFiled: April 19, 2018Date of Patent: November 19, 2019Assignees: TOYOTA JIDOSHA KABUSHII KAISHA, Tokyo University of Science FoundationInventors: Junichi Deguchi, Takahiro Shiina, Kensuke Yoshizue, Nobukazu Hoshi, Yusuke Kobayashi, Yosuke Murakami, Tomoya Abe
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Patent number: 10453954Abstract: In a termination structure region, a first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of a semiconductor substrate, is provided on the substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on a first side of the first semiconductor layer, opposite to a second side facing the substrate. Trenches penetrate the second semiconductor layer. At the first side in the first semiconductor layer, a first semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is provided at a side closer to an active region, contacting the second semiconductor layer. A second semiconductor region of the first conductivity type is provided in the second semiconductor layer, outside and adjacent to one of the trenches that is disposed at a farthest position from the active region.Type: GrantFiled: June 28, 2018Date of Patent: October 22, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masanobu Iwaya, Yasuhiko Oonishi, Yusuke Kobayashi
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Patent number: 10450218Abstract: The present invention relates to a vehicle-mounted display device disposed in an interior member of a vehicle. The vehicle-mounted display device of the invention includes: a display panel; a cover glass covering the display panel; a housing accommodating the display panel; and a holding portion holding a position of the housing, in which the cover glass is a tempered glass having a thickness being 0.5 to 2.5 mm, a thickness of a compressive stress layer being 10 ?m or more, and a surface compressive stress of a compressive layer being 650 MPa or higher, and when the thickness (unit: mm) of the cover glass is represented by x and an energy absorption rate (unit: %) of the holding portion is represented by y. Expression (1) is satisfied, and impact resistance of the cover glass is excellent: y??37.1×ln(x)+53.7??(1).Type: GrantFiled: November 14, 2017Date of Patent: October 22, 2019Assignee: AGC Inc.Inventors: Kyohei Hashimoto, Atsushi Inoue, Yasuhiro Inoue, Yasumasa Kato, Yasuji Fukasawa, Yusuke Kobayashi, Masaaki Konishi
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Patent number: 10434407Abstract: Provided is a game system capable of imposing restriction upon the beneficial effects of the characteristics of a character that has been selected. This game system is provided with control panels having individual rotational buttons. The game system provides a music game in which operation timings at which the individual rotational buttons are to be operated are guided in accordance with the rhythm of a musical piece selected from a musical piece group. Furthermore, the game system awards card selection opportunities for selecting character cards to be used in play, from a plurality of character cards prepared so as to have a plurality of skills which are different to each other, and which respectively correspond to changes. In a special mode, the game system sequentially implements, in a prescribed order every time the special mode is offered, the changes corresponding to the skills of the respective selected character cards.Type: GrantFiled: December 13, 2017Date of Patent: October 8, 2019Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.Inventors: Masahiro Kiyomoto, Koichi Tomita, Toyokazu Sakai, Shohei Sakuraba, Erina Takeda, Toru Miki, Atsushi Usami, Kanae Kokutani, Naotaka Okamoto, Yusuke Kobayashi
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Publication number: 20190293121Abstract: A structure including a sliding layer that is formed on a roughened surface of a substrate and that has an excellent slidability, and a method for producing the structure. The sliding layer is formed of a powder of a carbon-composition-containing resin composition filled in at least concavities of roughness on the roughened surface.Type: ApplicationFiled: June 1, 2017Publication date: September 26, 2019Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.Inventors: Kazunobu WATANABE, Toshinori ENOKIDO, Kouta SEGAMI, Yusuke KOBAYASHI
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Publication number: 20190280118Abstract: A first p+-type region in contact with a bottom of a gate trench is disposed in a striped shape extending along a first direction that is orthogonal to a second direction along which the gate trench extends in a striped shape, as viewed from a front surface of a silicon carbide substrate. As a result, trench gate MOSFETs are disposed in parallel at a predetermined cell pitch along the first direction. A flat SBD is disposed at a predetermined cell pitch along the second direction. The cell pitch of the trench gate MOSFET and the cell pitch of the flat SBD may be set independently of each other.Type: ApplicationFiled: February 25, 2019Publication date: September 12, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yusuke KOBAYASHI, Naoyuki OHSE
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Patent number: 10396194Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a Schottky electrode. Between trenches where the Schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region. A region of a part of the Schottky electrode faces toward the first semiconductor region in a depth direction and the trench faces the first semiconductor region in the depth direction.Type: GrantFiled: December 18, 2017Date of Patent: August 27, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yusuke Kobayashi
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Patent number: 10374080Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.Type: GrantFiled: April 2, 2018Date of Patent: August 6, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoyuki Ohse, Yusuke Kobayashi, Takahito Kojima, Shinsuke Harada
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Publication number: 20190235304Abstract: The present invention relates to a glass plate including a first main surface subjected to antiglare treatment, and a second main surface opposed to the first main surface, in which a clarity index value T, a reflection image diffusiveness index value R and an anti-sparkle index value S satisfy respective relations of: clarity index value T?0.8; reflection image diffusiveness index value R?0.01; and anti-sparkle index value S?0.85; and a transmission haze measured by a method according to JIS K 7136 (2000) being 15% or less. The glass plate of the present invention is excellent in clarity, reflection image diffusiveness and anti-sparkle, and also excellent in reproducibility of color.Type: ApplicationFiled: January 18, 2019Publication date: August 1, 2019Applicant: AGC Inc.Inventors: Minoru Tamada, Yusuke Kobayashi
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Patent number: 10361299Abstract: In an n-type current diffusion region, a first p+-type region is provided under a bottom of a trench (gate trench). Further, in the n-type current diffusion region, a second p+-type region is provided between adjacent trenches so as to be separated from the first p+-type region and in contact with a p-type base region. In the p-type base region, a third p+-type region is provided near a side wall of the trench so as to be separated from the trench and first and second p+-type regions. A depth of the third p+-type region from an interface of the p-type base region and an n+-type source region does not reach the n-type current diffusion region. A shortest distance from the third p+-type region to the second p+-type region is at most a distance between the first and second p+-type regions.Type: GrantFiled: July 23, 2018Date of Patent: July 23, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Shinsuke Harada
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Patent number: 10336380Abstract: A rocker bogie includes a first base which including a first wheel, a second wheel, and a third wheel each of which is configured to be in contact with a first flat surface, a second base including a fourth wheel which is configured to be in contact with the first flat surface, and a rotary shaft connecting the first base and the second base to each other such that the second base is rotatable with respect to the first base. The rotary shaft is parallel to a first straight line which connects a rotation center of the first wheel and a rotation center of the second wheel to each other and is disposed between a rotation center of the third wheel and the first straight line, and the fourth wheel is disposed at an opposite position to the third wheel across the first straight line.Type: GrantFiled: March 24, 2016Date of Patent: July 2, 2019Assignee: Tokyo Metropolitan Industrial Technology Research InstituteInventors: Kazuhiro Sakashita, Yusuke Morita, Toshiki Masuda, Yusuke Kobayashi
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Patent number: 10331417Abstract: Automatic verification of changes in a UML model made based on a change plan using a learning mode and a verification mode. In the learning mode, UML model differences are obtained between the UML model prior to the change and after the change, difference mapping is defined and a mapping metamodel is automatically extracted from the difference mapping. In the verification mode, planned difference mapping is created based on applying the mapping metamodel in the learning mode to a design change plan. Actual difference mapping based on the design change work is created and the planned difference mapping is compared to the actual difference mapping to see if additional changes to the mapping metamodel are needed.Type: GrantFiled: April 5, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Yusuke Kobayashi, Kiyonori Komiya, Takashi Nerome, Shuhichi Saitoh, Toshiaki Yasue
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Publication number: 20190189693Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.Type: ApplicationFiled: February 22, 2019Publication date: June 20, 2019Applicant: Toshiba Memory CorporationInventors: Yusuke KOBAYASHI, Yoshihisa IWATA, Takeshi SUGIMOTO
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Patent number: 10310142Abstract: There is provided an optical device including a display device, and a transparent substrate that is disposed on a side of a display surface of the display device. When the transparent substrate is evaluated by using a three index values of a resolution index value T, a reflection image diffusiveness index value R, and a sparkle index value S, the following conditions are satisfied: the resolution index value T?0.2, the reflection image diffusiveness index value R?0.2, and the sparkle index value S?60.Type: GrantFiled: July 14, 2015Date of Patent: June 4, 2019Assignee: AGC Inc.Inventors: Minoru Tamada, Yusuke Kobayashi, Tomonobu Senoo