Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: A vertical MOSFET having a trench gate structure includes a p-type base layer and an n?-type drift layer formed by epitaxial growth. In the n?-type drift layer, an n-type region and a first p+-type region are provided. The n-type region is constituted by a lower n-type region and an upper n-type region that is in contact with the lower n-type region and has an impurity concentration lower than that of the lower n-type region. The lower n-type region is partially provided between trenches and between first p+-type regions.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A p-type base region is constituted by first to fifth p-type base regions. The first p-type base region is provided deeper than gate trenches. The second p+-type base region is provided along side walls of a contact trench. The fourth p+-type base region is provided along a bottom of the contact trench and is exposed at the bottom of the contact trench. The fifth p-type base region is in contact with the second and fourth p+-type base regions, which have an impurity concentration higher than that of the fifth p-type base region. The fifth p-type base region is provided along the bottom of the contact trench and deeper than the fourth p+-type base region. In the fifth p-type base region, the third p++-type base region, which has an impurity concentration higher than that of the fifth p-type base region, is arranged.

Abstract: A capacitive three-dimensional sensor includes: a light-guide unit having a side surface and an operation surface, the side surface being formed along the Z direction and including a light entering portion, through which light from a light source enters, the operation surface being configured to input the inputs and including a light output portion, from which the light exits; a sheet-like X-Y electrode body configured to sense the inputs in the plane X and Y directions; a deformable body including a sheet-like elastic body; and a sheet-like Z electrode body configured to sense the input in the Z direction. The light-guide unit includes an optional decorative sheet, and a light-guide sheet to guide the light that has entered the light-guide unit from the side surface and output the light toward the light output portion. A total of bending stiffnesses of the light-guide sheet and decorative sheet is less than 256.

Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.

Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

Abstract: At bottom of a gate trench, a conductive layer is provided. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and the n-type current spreading region. The Schottky junction constitutes one unit cell of a trench-type SBD. In the gate trench, a gate electrode is provided on the conductive layer, via an insulating layer. The gate electrode constitutes one unit cell of a trench-gate-type vertical MOSFET. In other words, one unit cell of the trench gate MOSFET and one unit cell of the trench-type SBD are disposed built into a single gate trench and oppose each other in a depth direction.

Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.

Abstract: There is provided a communication relay device including at least one memory, and at least one processor coupled to the at least one memory, respectively, and the at least one processor configured to relay messages exchanged between a first wireless-base-station and a first wireless-network-side-device, or between a second wireless-base-station and a second wireless-network-side-device, acquire, from the messages, first and second statistic-information related to call processing between first and second wireless-base-stations and first and second wireless-network-side-devices, respectively, determine, in accordance with a number of first and second terminal-devices coupled to the first and second wireless-base-stations, respectively, included in first second statistic-information, respectively, an order of establishment of first and second communication sessions between the first and second wireless-base-stations and the first and second wireless-network-side-devices, respectively, and establish, when switchi

Abstract: In an n-type current diffusion region, a first p+-type region is provided under a bottom of a trench (gate trench). Further, in the n-type current diffusion region, a second p+-type region is provided between adjacent trenches so as to be separated from the first p+-type region and in contact with a p-type base region. In the p-type base region, a third p+-type region is provided near a side wall of the trench so as to be separated from the trench and first and second p+-type regions. A depth of the third p+-type region from an interface of the p-type base region and an n+-type source region does not reach the n-type current diffusion region. A shortest distance from the third p+-type region to the second p+-type region is at most a distance between the first and second p+-type regions.

Abstract: In an n-type current diffusion region, a first p30-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p30-type region is provided between adjacent trenches, separated from the first p30-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p30-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p30-type regions. The third p30-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p30-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

Abstract: In a termination structure region, a first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of a semiconductor substrate, is provided on the substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on a first side of the first semiconductor layer, opposite to a second side facing the substrate. Trenches penetrate the second semiconductor layer. At the first side in the first semiconductor layer, a first semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is provided at a side closer to an active region, contacting the second semiconductor layer. A second semiconductor region of the first conductivity type is provided in the second semiconductor layer, outside and adjacent to one of the trenches that is disposed at a farthest position from the active region.

Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.

Abstract: Provided is a writing implement capable of drawing lines using capillary action, wherein the width of the line can be freely adjusted while the line is being drawn and it is possible to draw lines of almost the same width at the beginning of the use of the writing implement as at the end of use. A felt-tip pen 1 is provided with an ink reservoir 11, a collector 17, and a core 29 for drawing by capillary action the ink that has been dispensed by the collector 17, dispensing the drawn ink from the tip, and adhering same to a paper surface. Even in repetitive writing, the rate of variability in the width of the lines drawn at the end of use with respect to the width of lines drawn at the beginning of use is 10% or less.

Abstract: A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.