Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.

Abstract: A first p+-type region in contact with a bottom of a gate trench is disposed in a striped shape extending along a first direction that is orthogonal to a second direction along which the gate trench extends in a striped shape, as viewed from a front surface of a silicon carbide substrate. As a result, trench gate MOSFETs are disposed in parallel at a predetermined cell pitch along the first direction. A flat SBD is disposed at a predetermined cell pitch along the second direction. The cell pitch of the trench gate MOSFET and the cell pitch of the flat SBD may be set independently of each other.

Abstract: A capacitive three-dimensional sensor includes: a light-guide unit having a side surface and an operation surface, the side surface being formed along the Z direction and including a light entering portion, through which light from a light source enters, the operation surface being configured to input the inputs and including a light output portion, from which the light exits; a sheet-like X-Y electrode body configured to sense the inputs in the plane X and Y directions; a deformable body including a sheet-like elastic body; and a sheet-like Z electrode body configured to sense the input in the Z direction. The light-guide unit includes an optional decorative sheet, and a light-guide sheet to guide the light that has entered the light-guide unit from the side surface and output the light toward the light output portion. A total of bending stiffnesses of the light-guide sheet and decorative sheet is less than 256.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: A semiconductor device includes: a first-conductivity-type drift layer including a first-conductivity-type impurity, vacancy-oxygen-hydrogen complex defects each caused by a vacancy, an oxygen atom, and a hydrogen atom, divacancy-and-vacancy-phosphorus complex defects, having a trap density level lower than a trap density level of the vacancy-oxygen-hydrogen complex defect, and third complex defects; a plurality of donor layers provided at different depths in a depth direction of the first-conductivity-type drift layer, wherein each of the plurality of donor layers includes donors caused by the vacancy-oxygen-hydrogen complex defects, and each of the plurality of donor layers has an impurity concentration distribution that includes a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both main surfaces of the first-conductivity-type drift layer; and a second-conductivity-type semiconduc

Abstract: In an n-type current diffusion region, a first p+-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p+-type region is provided between adjacent trenches, separated from the first p+-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p+-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p+-type regions. The third p+-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p+-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: A curable composition of the present invention includes a cationic polymerizable compound; a thermal polymerization initiator; and a storage stabilizer, in which the cationic polymerizable compound includes at least two selected from the group consisting of a glycidyl ether compound, an alicyclic epoxy compound, and an oxetane compound, a content of the thermal polymerization initiator is from 0.3 to 3 parts by mass with respect to 100 parts by mass of the cationic polymerizable compound, and chain curing is enabled by thermal energy generated by a polymerization reaction of the cationic polymerizable compound.

Abstract: A curved substrate with a film includes a substrate having a first main surface, a second main surface and an end surface, and an antiglare film provided on the first main surface. The substrate has a flat portion and a bent portion. A value obtained by dividing a reflected-image diffusibility index value R of the bent portion by the sum of the reflected-image diffusibility index value R of the bent portion and a reflected-image diffusibility index value R of the flat portion is 0.3 or higher and 0.8 or less.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: A composition containing 40 to 350 parts by weight of a functional fiber and 100 to 600 parts by weight of an inorganic microparticulate filler having an average particle diameter of less than 15 ?m per 100 parts by weight of the addition-reaction type polyimide resin. Also disclosed is a sliding member including the composition and a method for producing a molded article including the composition.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

Abstract: According to one embodiment, an ultrasonic probe includes a plurality of ultrasonic transducers, an electronic circuit, an insulative heat conductive spacer and an electrical heat supporting element. The electronic circuit is electrically connected to a plurality of transducers on one side. The insulative heat conductive spacer contacts with another side of the electronic circuit. The electrical heat supporting element has a contact region that makes contact, in a first surface, with the insulative heat conductive spacer, and a supporting structure that supports the insulative heat conductive spacer to have a predetermined thickness, and diffuses heat generated by the electronic circuit from the contact region.

Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.

Abstract: A transparent substrate having an antiglare function includes first and second faces. The transparent substrate has a resolution index value T, a reflected image diffusivity index value R, and a sparkle index value S satisfying T?0.25, R?0.8, and 0.75?S?0.95, respectively. The resolution index value T is calculated as (luminance of zero-degrees transmission light)/(luminance of total transmission light). The reflected image diffusivity index value R is calculated as (R2+R3)/(2×R1), where R1 denotes a luminance of reflected light reflected at first angle ?1, and R2, R3 denote luminance of reflected light at the second angle ?2, the third angle ?3, respectively, with respect to the first angle ?1. The sparkle index value S is calculated as 1?(Sa/Ss), where the first sparkle Sa and the second sparkle Ss denote a sparkle value of the transparent substrate and a sparkle value of a glass substrate, respectively.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.