Patents by Inventor Yusuke Kobayashi
Yusuke Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210183995Abstract: A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.1×1016/cm3 to 5.0×1016/cm3.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, KABUSHIKI KAISHA TOSHIBAInventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinya KYOGOKU, Shinsuke HARADA
-
Patent number: 11033249Abstract: An external ultrasonic probe includes a transducer array including multiple transducers arranged along an azimuth direction, the multiple transducers transmitting and receiving ultrasonic waves; and a covering material having a projecting surface touchable with a living body, formed of a single member, covering an entire front-surface side of the transducer array, and covering at least a part of a side-surface side of the transducer array. In a section dividing a width of the transducer array in the azimuth direction substantially into two equal parts, a width between two points on the projecting surface falling down from a top of the projecting surface by 2 mm is larger than a width of the transducer array in an elevation direction. A difference between the width between the two points and the width of the transducer array in the elevation direction is 5 mm or less.Type: GrantFiled: May 31, 2016Date of Patent: June 15, 2021Assignee: CANON MEDICAL SYSTEMS CORPORATIONInventors: Hiroyuki Shikata, Yusuke Kobayashi
-
Publication number: 20210175339Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region.Type: ApplicationFiled: September 10, 2020Publication date: June 10, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Hiro Gangi, Yusuke Kobayashi, Kentaro Ikeda, Tatsunori Sakano, Ryosuke Iijima
-
Publication number: 20210158230Abstract: The control apparatus includes a controller configured to acquire time slot data indicating an available time slot at a place that provides a service, and generate announcement data announcing a proposal to take a user to the place using a vehicle should the user reserve the time slot indicated by the time slot data, and a communication interface configured to transmit the announcement data generated by the controller to a terminal apparatus configured to present content of data to the user.Type: ApplicationFiled: November 23, 2020Publication date: May 27, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Chikage KUBO, Yusuke KOBAYASHI, Minoru KUBOTA, Kentaro TAKAHASHI, Hideo HASEGAWA, Takashi HORIGUCHI
-
Publication number: 20210147279Abstract: A supporting glass substrate includes a compression stress layer on a surface thereof, and has an average thermal expansion coefficient at 50° C. to 200° C. that is 7 ppm/° C. to 15 ppm/° C., an internal tensile stress that is 5 MPa to 55 MPa, and a depth of the compression stress layer that is 10 ?m to 60 ?m.Type: ApplicationFiled: November 9, 2020Publication date: May 20, 2021Applicant: AGC Inc.Inventors: Yusuke KOBAYASHI, Izuru KASHIMA, Kazutaka ONO, Seiji INABA, Hirofumi YAMAMOTO, Kiyoshi TAMAI
-
Patent number: 10966628Abstract: According to one embodiment, an ultrasound diagnosis apparatus is configured to generate ultrasound image data of a subject through an ultrasound probe. The ultrasound diagnosis apparatus includes a specifying unit, a transmission/reception condition change unit, and an image generator. The specifying unit specifies a characteristic site, which is included in a scanning range related to the ultrasound image data and has specific acoustic characteristics, based on three-dimensional image data of the subject generated in advance. The transmission/reception condition change unit changes transmission/reception conditions of ultrasound waves based on the acoustic characteristics of the characteristic site. The image generator generates the ultrasound image data based on changed transmission/reception conditions.Type: GrantFiled: October 23, 2015Date of Patent: April 6, 2021Assignee: Canon Medical Systems CorporationInventors: Takashi Takeuchi, Yusuke Kobayashi
-
Publication number: 20210098621Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yusuke KOBAYASHI, Shinsuke Harada, Takahito Kojima
-
Publication number: 20210083184Abstract: A semiconductor storage device includes a first wiring, a second wiring, an insulating portion, and a resistance changing film. The first wiring extends in a first direction. The second wiring extends in a second direction intersecting the first direction, and is provided at a location different from that of the first wiring in a third direction intersecting the first direction and the second direction. The insulating portion is provided between the first wiring and the second wiring in the third direction. The resistance changing film is provided between the first wiring and the second wiring in the third direction, is adjacent to the insulating film from a first side and a second side which is opposite to the first side in the first direction, and the resistance changing film being smaller than the second wiring in the first direction.Type: ApplicationFiled: September 2, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventor: Yusuke KOBAYASHI
-
Publication number: 20210083008Abstract: A semiconductor storage device includes a first wiring, a second wiring, an insulating film, a variable resistance film, and an insulating portion. The first wiring extends in a first direction. The second wiring extends in a second direction intersecting the first direction and is provided at a position different from the first wiring in a third direction intersecting the first direction and the second direction. The insulating film is provided between the first wiring and the second wiring in the third direction. The variable resistance film is provided between the first wiring and the second wiring in the third direction and is adjacent to the insulating film in the first direction. The insulating portion includes a portion provided between the first wiring and the second wiring in the third direction and is adjacent to the first insulating film from a side opposite to the variable resistance film.Type: ApplicationFiled: September 2, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventor: Yusuke KOBAYASHI
-
Patent number: 10910980Abstract: In a control device for a switched reluctance motor, a voltage drop control is executed in which a voltage dropped to be lower than a voltage applied in a case where the switched reluctance motor is driven in a high-load region is applied to the switched reluctance motor, in a case where the switched reluctance motor is driven in a low-load region. The low-load region is a lower load region than the high-load region.Type: GrantFiled: October 2, 2017Date of Patent: February 2, 2021Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, Tokyo University of Science FoundationInventors: Junichi Deguchi, Makoto Funahashi, Kensuke Yoshizue, Nobukazu Hoshi, Tomoya Abe, Yusuke Kobayashi, Yosuke Murakami
-
Publication number: 20210028276Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.Type: ApplicationFiled: September 30, 2020Publication date: January 28, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yusuke KOBAYASHI, Yasuhiko Oonishi, Masanobu Iwaya
-
Patent number: 10903351Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.Type: GrantFiled: October 23, 2018Date of Patent: January 26, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Shinsuke Harada, Takahito Kojima
-
Patent number: 10886365Abstract: A silicon carbide semiconductor device has an n-type drift layer provided on a front surface of an n+-type silicon carbide substrate. In a surface layer of the n-type drift layer, a first p+-type region is provided. On a front surface side of the n+-type silicon carbide substrate, a trench is formed. The first p+-type region includes a deep first p+-type region and a shallow first p+-type region, the deep first p+-type region being at a position farther toward a drain electrode than a bottom of the trench is and the shallow first p+-type region being at a position closer to a source region than the bottom of the trench is. An impurity concentration of the shallow first p+-type region is lower than an impurity concentration of the deep first p+-type region.Type: GrantFiled: July 25, 2017Date of Patent: January 5, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tsuyoshi Araoka, Yusuke Kobayashi
-
Patent number: 10840326Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a first semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a third semiconductor layer of the second conductivity type in the active region and a third semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the third semiconductor layer, and the second semiconductor layer is not in contact with a surface of the first semiconductor layer.Type: GrantFiled: July 26, 2017Date of Patent: November 17, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Yasuhiko Oonishi, Masanobu Iwaya
-
Publication number: 20200353727Abstract: A fiber-reinforced laminate including at least a layer of woven fibers and a layer of short fiber-containing resin composition, wherein the short fiber-containing resin composition is present in gaps formed by crossing fiber bundles composing the woven fibers. Also disclosed is a method for producing the laminate.Type: ApplicationFiled: November 27, 2018Publication date: November 12, 2020Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.Inventors: Kouta SEGAMI, Kazunobu WATANABE, Toshinori ENOKIDO, Yusuke KOBAYASHI
-
Publication number: 20200347488Abstract: Ti, N, Al, Mg, and Ca concentrations are controlled in order to prevent aggregation of TiN inclusions. Furthermore, not only is a Fe—Cr—Ni alloy having superior surface property provided, but also a method is proposed in which the Fe—Cr—Ni alloy is produced at low cost using commonly used equipment. The Fe—Cr—Ni alloy includes C?0.05%, Si: 0.1 to 0.8%, Mn: 0.2 to 0.8%, P?0.03%, S?0.001%, Ni:16 to 35%, Cr: 18 to 25%, Al: 0.2 to 0.4%, Ti: 0.25 to 0.4%, N?0.016%, Mg: 0.0015 to 0.008%, Ca?0.005%, O: 0.0002 to 0.005%, freely selected Mo: 0.5 to 2.5% in mass % and Fe and inevitable impurities as the remainder, wherein Ti and N satisfy % N×% Ti?0.0045 and the number of TiN inclusions not smaller than 5 ?m is 20 to 200 pieces/cm2 at a freely selected cross section.Type: ApplicationFiled: June 21, 2017Publication date: November 5, 2020Applicant: Nippon Yakin Kogyo Co., Ltd.Inventors: Kenji MIZUNO, Hidekazu TODOROKI, Yosuke BABA, Yusuke KOBAYASHI, Waki NISHIJIMA
-
Patent number: 10816840Abstract: The present invention relates to a glass plate including a first main surface subjected to antiglare treatment, and a second main surface opposed to the first main surface, in which a clarity index value T, a reflection image diffusiveness index value R and an anti-sparkle index value S satisfy respective relations of: clarity index value T?0.8; reflection image diffusiveness index value R?0.01; and anti-sparkle index value S?0.85; and a transmission haze measured by a method according to JIS K 7136 (2000) being 15% or less. The glass plate of the present invention is excellent in clarity, reflection image diffusiveness and anti-sparkle, and also excellent in reproducibility of color.Type: GrantFiled: January 18, 2019Date of Patent: October 27, 2020Assignee: AGC Inc.Inventors: Minoru Tamada, Yusuke Kobayashi
-
Publication number: 20200297308Abstract: In an ultrasound automatic scanning system according to an embodiment, one or more ultrasound probes transmit and receive an ultrasound wave. A mechanical mechanism holds the ultrasound probe and moves the ultrasound probe while a surface of the ultrasound probe is directed toward a subject. Processing circuitry detects, based on the ultrasound wave, distance information between a body surface and the surface of the ultrasound probe, with respect to a first scan position and a second scan position set along the body surface. The processing circuitry controls ultrasound scans performed in the first scan position and in the second scan position by the ultrasound probe moved by the mechanical mechanism based on the distance information. The processing circuitry controls the mechanical mechanism so as to move the ultrasound probe to the second scan position after the distance information detection and the ultrasound scan in the first scan position are performed.Type: ApplicationFiled: March 19, 2020Publication date: September 24, 2020Applicant: CANON MEDICAL SYSTEMS CORPORATIONInventors: Yusuke KOBAYASHI, Kengo OKADA
-
Patent number: 10770581Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.Type: GrantFiled: July 22, 2019Date of Patent: September 8, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoki Kumagai
-
Patent number: 10770582Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.Type: GrantFiled: July 22, 2019Date of Patent: September 8, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai