Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract: A vehicle heating and air conditioning system basically includes an interior/exterior air introducing structure, a heating device, a driving end time acquiring section and an interior/exterior air switching control section. The interior/exterior air introducing structure switches the flow of cabin intake air between an interior air recirculation mode and an exterior air introducing mode. The heating device heats the cabin intake air being introduced by the interior/exterior air introducing structure. The driving end time acquiring section estimates a driving end time corresponding to a point in time at which driving of a vehicle is predicted to end. The interior/exterior air switching control section switches the interior/exterior air introducing structure from the exterior air introducing mode to the interior air recirculation mode during a period of time from a prescribed point in time until the driving end time to restrict windshield fogging while in the interior air recirculation mode.

Abstract: An air conditioner for a vehicle includes: a compressor (21); an internal heat exchanger (22, 24) which exchanges heat between the refrigerant and air in an interior space; an external heat exchanger (23) which exchanges heat between the refrigerant and outside air; a battery (5); a battery heat exchanger (29) which exchanges heat between the refrigerant and the battery by causing the refrigerant, which travels to the compressor from the external heat exchanger, to go through the battery heat exchanger; a throttle adjusting part (30) which is arranged in a refrigerant flow passage on an upstream side of the battery heat exchanger; and a control unit (40). The control unit (40) controls the flow of the refrigerant through the throttle adjusting part based on an extra heat exchange capacity that is an extra capacity of the external heat exchanger with respect to the internal heat exchanger.

Abstract: Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit.

Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

Abstract: A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed. The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

Abstract: A noise current passing through a substrate on which an electronic component is mounted is suppressed in a housing, to provide a malfunction of an electronic device. A substrate (103) on which an electronic component is mounted is secured to a housing (102) by a metal spacer (108) and a screw (104). A noise control member (100) mainly composed of an insulation substance is disposed between the metal spacer (108) and the substrate (103). A first conductive film is formed on the metal spacer-side of the noise control member (100), and a second conductive film is formed on the substrate-side of the noise control member (100). A resistance member (101) is disposed between the first conductive film and the second conductive film. A noise current introduced from the housing to the substrate can be suppressed by the resistance member.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: In an environment in which signal-to-noise is poor, a method and a system configuration for power-saving, low-cost, and general minute signal detection are provided.

Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.

Abstract: A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: A signal transmission system is provided which connects a memory controller and a plurality of semiconductor memories. The signal transmission system comprises a semiconductor device arranged between the memory controller and the plurality of memories, in which: the semi-conductor device comprises a control circuit; and the control circuit receives a signal from the semiconductor memory and outputs a control signal to the memory controller in response to the signal from the semiconductor memory.

Abstract: A signal transmission system is provided which connects a memory controller and a plurality of semiconductor memories. The signal transmission system comprises a semiconductor device arranged between the memory controller and the plurality of memories, in which: the semi-conductor device comprises a control circuit; and the control circuit receives a signal from the semiconductor memory and outputs a control signal to the memory controller in response to the signal from the semiconductor memory.

Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.