Patents by Inventor Yutaka Uematsu

Yutaka Uematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8633596
    Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: January 21, 2014
    Inventors: Mitsuaki Katagiri, Ken Iwakura, Yutaka Uematsu
  • Publication number: 20130307582
    Abstract: To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Satoshi Muraoka
  • Patent number: 8581622
    Abstract: To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Satoshi Muraoka
  • Publication number: 20130207234
    Abstract: A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.
    Type: Application
    Filed: August 15, 2012
    Publication date: August 15, 2013
    Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Satoshi Muraoka
  • Publication number: 20130199217
    Abstract: An air conditioner for a vehicle includes: a compressor (21); an internal heat exchanger (22, 24) which exchanges heat between the refrigerant and air in an interior space; an external heat exchanger (23) which exchanges heat between the refrigerant and outside air; a battery (5): a battery heat exchanger (29) which exchanges heat between the refrigerant and the battery by causing the refrigerant, which travels to the compressor from the external heat exchanger, to go through the battery heat exchanger; a throttle adjusting part (30) which is arranged in a refrigerant flow passage on an upstream side of the battery heat exchanger; and a control unit (40). The control unit (40) controls the flow of the refrigerant through the throttle adjusting part based on an extra heat exchange capacity that is an extra capacity of the external heat exchanger with respect to the internal heat exchanger.
    Type: Application
    Filed: September 27, 2011
    Publication date: August 8, 2013
    Inventors: Fuijo Arai, Yutaka Uematsu
  • Publication number: 20130112390
    Abstract: A vehicle heating and air conditioning system basically includes an interior/exterior air introducing structure, a heating device, a driving end time acquiring section and an interior/exterior air switching control section. The interior/exterior air introducing structure switches the flow of cabin intake air between an interior air recirculation mode and an exterior air introducing mode. The heating device heats the cabin intake air being introduced by the interior/exterior air introducing structure. The driving end time acquiring section estimates a driving end time corresponding to a point in time at which driving of a vehicle is predicted to end. The interior/exterior air switching control section switches the interior/exterior air introducing structure from the exterior air introducing mode to the interior air recirculation mode during a period of time from a prescribed point in time until the driving end time to restrict windshield fogging while in the interior air recirculation mode.
    Type: Application
    Filed: August 1, 2011
    Publication date: May 9, 2013
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Fujio Arai, Yutaka Uematsu, Takayoshi Matsuoka
  • Patent number: 8355258
    Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: January 15, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Osaka, Yutaka Uematsu
  • Publication number: 20120262885
    Abstract: Provided is a signal transfer circuit which uses a low cost circuit board with a high packing density but is capable of reducing a crosstalk noise between signal lines and also reducing a reflection noise due to a stub. A signal transfer circuit of the present invention is configured such that lead terminals of electronic components and through-hole vias are connected to each other by surface wirings, respectively, to allow no branching from the middle of the through-hole vias. Further, first wirings connecting a first electronic component are each arranged between a corresponding pair of second wirings connecting a second electronic component, and signals are transmitted through the first wirings and the second wirings by interleaved transmission.
    Type: Application
    Filed: January 26, 2012
    Publication date: October 18, 2012
    Inventors: Yasuhiro IKEDA, Yutaka Uematsu, Satoshi Muraoka
  • Patent number: 8288852
    Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: October 16, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Yukitoshi Hirose
  • Publication number: 20120200159
    Abstract: A semiconductor device includes: first and second power supply wirings VDDQ and VSSQ, respectively; an output circuit 12 arranged between VDDQ and VSSQ; and a noise cancellation circuit 13 arranged between VDDQ and VSSQ. The noise cancellation circuit 13 produces a damped oscillation for the SSN oscillation noise that is generated when a logic level outputted to an output node of the output circuit is switched and that exponentially damps and oscillates at a predetermined period. The damped oscillation produced by the noise cancellation circuit 13 is delayed by half a period of the SSN oscillation noise and has a direction opposite to that of the SSN oscillation noise and hence the damped oscillation and the SSN oscillation noise counteract each other.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 9, 2012
    Inventors: Mitsuaki KATAGIRI, Ken Iwakura, Yutaka Uematsu
  • Publication number: 20120119387
    Abstract: A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 17, 2012
    Inventors: Mitsuaki KATAGIRI, Ken Iwakura, Yutaka Uematsu
  • Publication number: 20120112849
    Abstract: A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed. The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).
    Type: Application
    Filed: January 11, 2011
    Publication date: May 10, 2012
    Inventors: Yasuhiro IKEDA, Yutaka UEMATSU, Satoshi MURAOKA
  • Publication number: 20110234249
    Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 29, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka UEMATSU, Hideki OSAKA, Satoshi NAKAMURA, Satoshi MURAOKA, Mitsuaki KATAGIRI, Ken IWAKURA, Yukitoshi HIROSE
  • Publication number: 20110239176
    Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: Hideki OSAKA, Yutaka UEMATSU
  • Publication number: 20110193215
    Abstract: Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Inventors: Masahiro TOYAMA, Yutaka UEMATSU, Hideki OSAKA
  • Patent number: 7990228
    Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 2, 2011
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Eiichi Suzuki
  • Patent number: 7986037
    Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: July 26, 2011
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Tatsuya Saito, Hideki Osaka, Yoji Nishio, Shunichi Saito
  • Patent number: 7965572
    Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 21, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Tatsuya Saito, Yoji Nishio, Yukitoshi Hirose
  • Patent number: 7957150
    Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Osaka, Yutaka Uematsu
  • Patent number: 7939907
    Abstract: High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideki Osaka, Yutaka Uematsu, Eiichi Suzuki