Patents by Inventor Yutaka Uematsu
Yutaka Uematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7889584Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.Type: GrantFiled: October 13, 2006Date of Patent: February 15, 2011Assignee: Elpida Memory Inc.Inventors: Yoji Idei, Susumu Hatano, Yoji Nishio, Seiji Funaba, Yutaka Uematsu
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Publication number: 20100321060Abstract: In a signal transmission system, performing signal transmission via signal interconnections 4-1 to 4-3 between a memory 1 and a memory controller 2 mounted on a printed circuit board 3, noise or jitter may tend to be increased in the memory 1 and in the memory controller 2 at a specified data rate due to interconnection length resonance. Registers 6-1 and 6-2 are provided to hold information on the data rate. These registers 6-1 and 6-2 are provided in the signal transmission system along with a control system that modifies the relationship between clock frequency and interconnection length. The data rate or the propagation delay time is controlled to allow for avoiding the resonance.Type: ApplicationFiled: June 16, 2010Publication date: December 23, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yoji Nishio, Yutaka Uematsu, Hideki Oosaka, Akihiro Namba, Satoshi Nakamura
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Patent number: 7852145Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.Type: GrantFiled: January 23, 2009Date of Patent: December 14, 2010Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Tatusya Saito, Yoji Nishio
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Patent number: 7816757Abstract: High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.Type: GrantFiled: May 30, 2007Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Hideki Osaka, Yutaka Uematsu, Eiichi Suzuki
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Patent number: 7768867Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: GrantFiled: June 12, 2007Date of Patent: August 3, 2010Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Yutaka Uematsu, Seiji Funaba, Hideki Osaka, Tsutomu Hara, Koichiro Aoki
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Patent number: 7760531Abstract: A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.Type: GrantFiled: August 29, 2006Date of Patent: July 20, 2010Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Seiji Funaba, Yutaka Uematsu, Hideki Osaka
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Publication number: 20100090325Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka UEMATSU, Yukitoshi HIROSE
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Publication number: 20100013528Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.Type: ApplicationFiled: July 16, 2009Publication date: January 21, 2010Applicant: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Tatsuya Saito, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20090213558Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.Type: ApplicationFiled: January 29, 2009Publication date: August 27, 2009Inventors: Hideki OSAKA, Yutaka Uematsu
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Publication number: 20090195295Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.Type: ApplicationFiled: January 23, 2009Publication date: August 6, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka Uematsu, Hideki Osaka, Tatusya Saito, Yoji Nishio
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Publication number: 20090189293Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.Type: ApplicationFiled: January 6, 2009Publication date: July 30, 2009Applicant: Elpida Memory, Inc.Inventors: Eiichi Suzuki, Hideki Osaka, Yutaka Uematsu, Yoji Nishio
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Publication number: 20080290495Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.Type: ApplicationFiled: February 8, 2008Publication date: November 27, 2008Inventors: Yutaka Uematsu, Tatsuya Saito, Hideki Osaka, Yoji Nishio, Shunichi Saito
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Patent number: 7447038Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.Type: GrantFiled: December 16, 2005Date of Patent: November 4, 2008Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Seiji Funaba
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Publication number: 20080266031Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.Type: ApplicationFiled: April 2, 2008Publication date: October 30, 2008Inventors: Yutaka UEMATSU, Hideki Osaka, Yoji Nishio, Eiichi Suzuki
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Publication number: 20080054379Abstract: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.Type: ApplicationFiled: February 15, 2007Publication date: March 6, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yoji Nishio, Yutaka Uematsu, Hideki Osaka, Tsutomu Hara, Seiji Funaba
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Patent number: 7319267Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.Type: GrantFiled: March 1, 2007Date of Patent: January 15, 2008Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20070291557Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: ApplicationFiled: June 12, 2007Publication date: December 20, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Yoji NISHIO, Yutaka UEMATSU, Seiji FUNABA, Hideki OSAKA, Tsutomu HARA, Koichiro AOKI
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Publication number: 20070289771Abstract: The present invention realizes high density mounting along with achieving power source sharing by a digital semiconductor element and an analog semiconductor element in a semiconductor device. An power layer for analog is connected to one end of an EBG layer, a power layer for digital is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog and the EBG layer from each other is disposed between the power layer for analog and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of power source to an analog chip.Type: ApplicationFiled: May 30, 2007Publication date: December 20, 2007Inventors: HIDEKI OSAKA, YUTAKA UEMATSU, EIICHI SUZUKI
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Publication number: 20070145559Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.Type: ApplicationFiled: March 1, 2007Publication date: June 28, 2007Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20070085601Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.Type: ApplicationFiled: October 13, 2006Publication date: April 19, 2007Inventors: Yoji Idei, Susumu Hatano, Yoji Nishio, Seiji Funaba, Yutaka Uematsu