Patents by Inventor Yu-Yu Lin

Yu-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12362014
    Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: July 15, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 12347481
    Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: July 1, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Ming-Hsiu Lee
  • Publication number: 20250210100
    Abstract: A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Inventors: Feng-Min LEE, Po-Hao TSENG, Yu-Yu LIN, Yu-Hsuan LIN, Wei-Fu WANG, Wei-Lun WENG
  • Publication number: 20250174273
    Abstract: The integrated circuit structure includes a substrate and a first resistive memory string over the substrate. The first resistive memory string includes memory cells, and each of the memory cells includes a word line transistor and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region. The resistor is over the word line transistor and is connected with the word line transistor in parallel. The word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Inventors: Yu-Yu LIN, Feng-Min LEE
  • Publication number: 20250149083
    Abstract: An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventor: Yu-Yu LIN
  • Patent number: 12277968
    Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: April 15, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Publication number: 20250111874
    Abstract: A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Yu-Hsuan LIN, Feng-Min LEE, Ming-Hsiu LEE, Yu-Yu LIN
  • Publication number: 20250095720
    Abstract: A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Yu-Hsuan LIN, Yu-Yu LIN, Feng-Min LEE
  • Publication number: 20250086443
    Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Macronix International Co., Ltd.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Ming-Hsiu Lee
  • Publication number: 20250022508
    Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Inventors: Yu-Yu LIN, Feng-Min LEE, Ming-Hsiu LEE
  • Patent number: 12198766
    Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 14, 2025
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Hsuan Lin, Yu-Yu Lin, Hsiang-Lan Lung
  • Patent number: 12198757
    Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 14, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 12182914
    Abstract: Disclosed is an image display format conversion method, comprising: a frame recognition step of performing a frame recognition process on a comic page image to obtain a plurality of comic frame images and frame position information; a frame sequence determination step of determining a frame viewing sequence according to a selected regional layout rule; and a frame reassembly step of reassembling and converting, based on the frame viewing sequence, the plurality of comic frame images into a digital media in an animation-like format or a scrolling-comic format.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: December 31, 2024
    Assignee: HYWEB TECHNOLOGY CO., LTD.
    Inventors: Chung-Wei Yu, Yu-Yu Lin
  • Publication number: 20240412784
    Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 12159672
    Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: December 3, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Yu-Hsuan Lin, Tian-Cih Bo, Feng-Min Lee, Yu-Yu Lin
  • Patent number: 12142316
    Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: November 12, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
  • Publication number: 20240371453
    Abstract: A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Inventors: Yu-Yu LIN, Feng-Min LEE
  • Publication number: 20240355387
    Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Yu-Yu LIN, Feng-Min LEE
  • Publication number: 20240311638
    Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Nien-Tzu Chou, Yu-Yu Lin, Ching-Fang Lu, Jian-Hao Li, Ting-Hsuan Chen, Cheng-Tai Chen
  • Publication number: 20240311620
    Abstract: A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Inventors: Yu-Yu LIN, Feng-Min LEE