Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming a bottom electrode layer on the base, wherein a crystal structure of the bottom electrode layer includes a tetragonal crystal system; forming a first dielectric layer on a surface of the bottom electrode layer by using the bottom electrode layer as a seed layer, wherein a crystal structure of the first dielectric layer includes a tetragonal crystal system; and forming a first current blocking layer on a surface of the first dielectric layer.

Abstract: A forming method for a semiconductor structure and the semiconductor structure are provided. The forming method of the semiconductor structure includes: providing a substrate, wherein separate bit line structures are formed on the substrate; forming a first sacrificial layer on a sidewall of a bit line structure; forming first dielectric layer filling gaps between adjacent bit line structures; patterning a first dielectric layer to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures; forming a second sacrificial layer on sidewalls of a via, and filling the via to form a contact plugs; forming a contact structure on the contact plug; and removing the first sacrificial layer to form first air gap, and removing the second sacrificial layer to form a second air gap.

Abstract: A semiconductor structure and a semiconductor structure manufacturing method is provided. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first storage structure and a second storage structure located on the two sides of the wordline, the first bitline and the second bitline being connected to the first storage structure and the second storage structure respectively through a transistor. An extension direction of the first bitline and an extension direction of the wordline are at an acute or obtuse angle. In this way, the first storage structure and the second storage structure are provided on both sides of the wordline, which can increase storage capacity.

Abstract: A method for forming a semiconductor structure and the semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a substrate, wherein a separate bit line structure is formed on the substrate; forming a first sacrificial layer on the side wall of the bit line structure; forming a first dielectric layer filling gap between the bit line structures; patterning the first dielectric layer and the first sacrificial layer to form a through hole, wherein the through hole and the remaining first dielectric layer and first sacrificial layer are alternately arranged; forming a second sacrificial layer on the side wall of the through hole, and filling the through hole to form a contact plug; forming a contact structure on the contact plug; and removing the first sacrificial layer to form a first air gap, and removing the second sacrificial layer to form a second air gap.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes: a base plate, configured to place a package chip to be injection-moulded, the package chip including a substrate and at least one chip fixed on a surface of the substrate by a flip chip process, the substrate having a through hole, a glue injection channel being formed in the base plate and configured to inject a moulding compound, and the glue injection channel being connected with the through hole on the substrate. The above-mentioned injection mould can improve the reliability of the package chip after injection moulding.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns; a plurality sets of rear conductive patterns; and a plurality sets of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; wherein the package substrate at least comprises a first thermal performance region and a second thermal performance region, wherein the first thermal performance region and the second thermal performance region have different thermal performances; a plurality sets of conductive components attached to the front surface and the rear surface of the package substrate and connected to the plurality sets of front conductive patterns and the plurality sets of rear conductive patterns, wherein the plurality sets of conductive components comprise: a set of first-type conductive components mounted to the first thermal performance region of

Abstract: A semiconductor package comprise: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a set of front conductive patterns formed on the front surface; a set of rear conductive patterns formed on the rear surface; and a set of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns via a set of front solder balls; a set of rear solder balls electrically connected to the set of rear conductive patterns, respectively; wherein the set of front solder balls comprises one or more first-type solder balls and one or more second-type solder balls, and the set of rear solder balls comprises one or more first-type solder balls and one or more second-type solder balls; and wherein the first-type solder balls of the set of front solder balls are elec

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the set of second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein

Abstract: Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.

Abstract: Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.

Abstract: Embodiments of the present application provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first memory structure and a second memory structure located on the two sides of the wordline. The first bitline and the second bitline are connected to the first memory structure and the second memory structure respectively through a transistor. An extension direction of the first bitline is perpendicular to an extension direction of the wordline.

Abstract: A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate with trenches, and the trenches extending along a thickness direction of the substrate from a first surface of the substrate; forming a first auxiliary layer and a first conductive layer successively in the trenches, and the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form first openings; forming a second medium layer on the second surface of the substrate; patterning the second medium layer to form second openings in the second medium layer, and the second openings exposing the first openings; and depositing a second initial conductive layer, the second initial conductive layer filling the first openings and the second openings.

Abstract: A semiconductor structure includes a base and a conductive channel structure, in which the conductive channel structure includes a base and a conductive channel structure which includes a first conductive channel layer including a first conductive channel, and a first and a second doped regions respectively located at two ends of the first conductive channel, a second conductive channel layer including a second conductive channel, and a third and a fourth doped regions respectively located at two ends of the second conductive channel and a conductive buffer layer configured to reduce electrical interference between the first and the third doped regions; a first conductive layer in contact with the second doped region; a second conductive layer nested on the conductive channel structure and in contact with the first and the third doped regions; and a gate structure arranged around the first conductive channel and the second conductive channel.

Abstract: An embodiment of the present application provides a manufacturing method of a semiconductor structure, including: providing a base; forming a first mask layer with a first mask pattern on the base, and etching the base with the first mask layer as a mask to form an active region; forming a plurality of discrete bitlines on the active region; sequentially stacking a first spacer layer and a second spacer layer on a side wall of the bitline; forming a sacrificial layer between the adjacent second spacer layers; forming a second mask layer with a second mask pattern on the sacrificial layer, the first mask pattern being complementary to the second mask pattern; etching the sacrificial layer with the second mask layer and the bitline as masks to form multiple contact hole structures; and etching the first spacer layer to form a gap between the second spacer layer and the bitline.

Abstract: Embodiments of the present application provide a semiconductor structure that comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface, a solder pad located at the first surface, a heat transfer layer located at the first surface and being in contact with the solder pad, and a groove located in the semiconductor substrate and being connected to the heat transfer layer.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Abstract: A contact window structure, a metal plug and a forming method thereof, a method of forming the contact window structure and a semiconductor structure are provided. In the method of forming the contact window, an annular pad is formed on a surface of a target layer. A central via, from which partial surface of the target layer is exposed, is formed in the middle part of the annular pad. A dielectric layer covering a substrate, the target layer and the annular pad is formed. The dielectric layer is etched to form an etch hole connected to the central via in the dielectric layer. The annular pad is removed along the etch hole and the central via to enlarge a size of the central via, so as to form the contact window structure by the etch hole and the central via with the enlarged size.