Abstract: The present invention provides a semiconductor manufacturing method. A substrate having a plurality of first trenches can be provided. The substrate can include a first pattern formed between two adjacent first trenches. A first dielectric layer can be deposited onto the substrate. The first dielectric layer can cover at least one side wall of the first pattern. A second dielectric layer can be deposited onto the substrate. The second dielectric layer can fill the first trenches. The first pattern can be severed to form a second pattern on the substrate. The second dielectric layer can be removed from the first trenches.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

Abstract: The present disclosure provides an electrostatic protection device and an electrostatic protection circuit. The electrostatic protection device includes: a discharge transistor, located on a substrate for discharging electrostatic charges; and a first pad, located on a first metal layer and electrically connected to a drain region of the discharge transistor; wherein a projection of the first pad on the substrate partially overlaps a projection of the drain region on the substrate.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.

Abstract: The present disclosure discloses a semiconductor memory preparation method and a semiconductor memory, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate in which transistors are formed and have an array layout; forming a film stack structure on the semiconductor substrate; forming through holes penetrating the film stack structure to expose sources of the transistors; epitaxially growing a storage node contact layer on exposed surfaces of the sources of the transistors; and forming a bottom electrode of a capacitor on a surface of the storage node contact layer.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes a base plate used to place a packaged chip to be injection moulded including a substrate and at least one of the chips fixed on the front substrate by a flip chip process. The substrate has a gas hole. Two or more gas ducts that extend in at least two intersected directions and connect with one another are formed in the base plate. Two ends of each one of gas ducts are open, and at least one of the gas ducts is buried into the base plate. Each one of gas ducts is provided with a gas outlet. When the packaged chip is placed on the base plate, the gas outlet connects with the gas hole of the substrate.

Abstract: An electrostatic discharge (ESD) protection circuit including a monitoring unit, a main discharge transistor, and an auxiliary discharge transistor is provided herein. The monitoring unit is configured to detect an electrostatic pulse caused by accumulation of electrostatic charges. The main discharge transistor and the auxiliary discharge transistor are configured discharge the electrostatic charges to ground end after the electrostatic pulse is detected. A first section of a power supply metal line is coupled to the main discharge transistor and the auxiliary discharge transistor, a third section of the power supply metal line is coupled to an internal circuit protected by the ESD protection circuit, and a second section of the power supply metal line couples the first section to the third section. The power supply metal line includes an angle that is less than 180 degrees at a contact position between the second section and the first section.

Abstract: The present disclosure in the field of memory technology proposes a programmable storage cell, a programmable storage array and a reading and writing method for the programmable storage array. The programmable storage cell includes: a first anti-fuse element connected between a first power terminal and an output terminal, a second anti-fuse element connected between the second power terminal and the output terminal, and a third switch unit connected to the output terminal, a third power terminal and a position signal terminal, where the third switch unit responds to the signal from the position signal terminal so as to connect the third power terminal and the output terminal. The programmable storage cell has a simple structure and a high reading speed.

Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

Abstract: A protection ring, a method for forming a protection ring, and a semiconductor structure are provided. The protection ring at least includes a buried protection structure. The buried protection structure is arranged in a semiconductor substrate. The buried protection structure is configured to protect a first functional structure formed inside the semiconductor substrate.

Abstract: A read-write circuit of a one-time programmable memory, including: an antifuse array including: n*n antifuse units, between a first node and a second node, the control terminals of switching elements in the antifuse units coupled to AND signals of different word line signals and bit line signals; the first switching device and the first capacitor connected in parallel between the second node and the second voltage source; the reference array including reference resistance and reference switching elements connected in series between the first and third nodes, the reference switching element's control end coupled to OR signals of the n*n AND signals; the second switching device and the second capacitor connected in parallel between the third node and second voltage source; a comparison circuit's first input terminal coupled to the second node and second input terminal coupled to the third node. The circuit has simpler connections, smaller area, and higher reliability.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Abstract: An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Abstract: The present disclosure discloses a semiconductor memory preparation method and a semiconductor memory, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate in which transistors are formed and have an array layout; forming a film stack structure on the semiconductor substrate; forming through holes penetrating the film stack structure to expose sources of the transistors; epitaxially growing a storage node contact layer on exposed surfaces of the sources of the transistors; and forming a bottom electrode of a capacitor on a surface of the storage node contact layer.

Abstract: An error correction system is disclosed. The error correction system is applied to a storage system. The error correction system generates X first operation codes, Y second operation codes and a third operation code based on the storage system. The error correction system includes an error state determining circuit and M decoding circuits. The error state determining circuit is configured to identify a current error state. When a plurality of pieces of data have a 1-bit error, the M decoding circuits are configured to execute decoding processing on the X first operation codes and the Y second operation codes, to obtain whether there is erroneous data in the bytes corresponding to the decoding circuits and locate a bit to which the erroneous data belongs.

Abstract: The present disclosure discloses a semiconductor device manufacturing method and a semiconductor device, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate, the semiconductor substrate comprising a shallow trench and active areas isolated from the shallow trench; forming an oxygen-containing layer on exposed outer surfaces of the shallow trench and the active areas; filling a first sacrificial layer of a set height in the shallow trench comprising the oxygen-containing layer on its surface; forming an etch stop layer on an upper surface of the first sacrificial layer; removing the first sacrificial layer below the etch stop layer to form an air gap; filling an isolation layer on the etch stop layer in the shallow trench to form a shallow trench isolation(STI) structure containing the air gap; and etching the active areas and the (STI) structure to form wordline trenches.