Abstract: The present disclosure provides a read-write method. The read-write method includes: when a write operation is performed on a memory, a number of first values and a number of second values in data to be written are determined; and if the number of first values is greater than the number of second values in the data to be written, the data to be written is inverted and then stored, and an identification bit is allocated, the identification bit stores a first mark to identify the data to be written.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

Abstract: The present disclosure provides a printed circuit board with a plated through hole. The through hole covered by a solder pad at both ends of the through hole. At least two pins are plugged into the through hole, one of which with its head end being thermal contacted with one of the solder pads. Another pin's head end being thermal contacted with the other solder pad. The at least two pins are thermal contacted with one another. Thermal dissipation rate is increased with the structure of the through hole.

Abstract: An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.

Abstract: An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Abstract: The disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure, relates to the field of semiconductor manufacturing technologies. The semiconductor structure includes: a substrate, having a bit line groove; a bit line, located in the bit line groove, and extending in a first direction; and a vertical transistor, located on the bit line. The bit line includes a bit line contact structure, and the bit line contact structure is a concave structure and/or a convex structure. The vertical transistor is electrically connected to the bit line by the bit line contact structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate with trenches, and the trenches extending along a thickness direction of the substrate from a first surface of the substrate; forming a first auxiliary layer and a first conductive layer successively in the trenches, and the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form first openings; forming a second medium layer on the second surface of the substrate; patterning the second medium layer to form second openings in the second medium layer, and the second openings exposing the first openings; and depositing a second initial conductive layer, the second initial conductive layer filling the first openings and the second openings.

Abstract: A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Abstract: The present disclosure discloses a semiconductor device manufacturing method and a semiconductor device, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate, the semiconductor substrate comprising a shallow trench and active areas; forming an oxygen-containing layer on exposed outer surfaces of the shallow trench and the active areas; filling a first isolation layer of a set height in the shallow trench comprising the oxygen-containing layer on its surface, the set height being lower than heights of the active areas; forming an etch stop layer on an upper surface of the first isolation layer; filling a second isolation layer on the etch stop layer in the shallow trench to form a shallow trench isolation (STI) structure; and etching the active areas and the STI structure to form wordline trenches, the bottoms of the wordline trenches in the STI structure are higher than the set height.

Abstract: The present application provides a method for manufacturing a memory and a memory, which relate to the technical field of memory devices and are used to solve the technical problems of relatively low storage speed and storage efficiency. The manufacturing method includes: providing a substrate, a plurality of capacitor contact pads being disposed at intervals in the substrate; forming a first recess on a first surface of each of the capacitor contact pads; forming conductive pillars in the first recesses, upper end surfaces of the conductive pillars being flush with the first surfaces of the capacitor contact pads; and forming a plurality of capacitors on the substrate, the plurality of the capacitors and the plurality of the capacitor contact pads corresponding one to one and being electrically connected; wherein a first plate of each of the capacitors covers the corresponding conductive pillar.

Abstract: An electrostatic discharge (ESD) protection circuit including a monitoring unit, a main discharge transistor, and an auxiliary discharge transistor is provided herein. The monitoring unit is configured to detect an electrostatic pulse caused by accumulation of electrostatic charges. The main discharge transistor and the auxiliary discharge transistor are configured discharge the electrostatic charges to ground end after the electrostatic pulse is detected. A first section of a power supply metal line is coupled to the main discharge transistor and the auxiliary discharge transistor, a third section of the power supply metal line is coupled to an internal circuit protected by the ESD protection circuit, and a second section of the power supply metal line couples the first section to the third section. The power supply metal line includes an angle that is less than 180 degrees at a contact position between the second section and the first section.

Abstract: The present disclosure discloses a semiconductor device manufacturing method and a semiconductor device, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate, the semiconductor substrate comprising a shallow trench and active areas; forming an oxygen-containing layer on exposed outer surfaces of the shallow trench and the active areas; filling a first isolation layer of a set height in the shallow trench comprising the oxygen-containing layer on its surface, the set height being lower than heights of the active areas; forming an etch stop layer on an upper surface of the first isolation layer; filling a second isolation layer on the etch stop layer in the shallow trench to form a shallow trench isolation (STI) structure; and etching the active areas and the STI structure to form wordline trenches, the bottoms of the wordline trenches in the STI structure are higher than the set height.

Abstract: A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Abstract: This application provides an electrostatic discharge protection circuit, disposed between a first pad and a second pad of a circuit. The electrostatic discharge protection circuit includes: a main discharge transistor and an auxiliary discharge transistor, both configured to be conductive after an electrostatic pulse caused by electrostatic charges is detected on the first pad to discharge the electrostatic charges to the second pad. Conduction time of the main discharge transistor is prior to conduction time of the auxiliary discharge transistor. An amount of the electrostatic charges discharged by the main discharge transistor is greater than an amount of the electrostatic charges discharged by the auxiliary discharge transistor. The circuit provided in this application can prolong bleeding of the electrostatic charges time and has a sufficient electrostatic discharge capability.

Abstract: A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a first transistor, located on the substrate; a second transistor, located above the first transistor; and a gate structure, the gate structure including a first gate layer and a second gate layer, which connected to each other, the first gate layer surrounding the first transistor and the second gate layer surrounding the second transistor; an extension direction of the first transistor and an extension direction of the second transistor are both perpendicular to the substrate.

Abstract: A semiconductor structure includes a base and a conductive channel structure, in which the conductive channel structure includes a base and a conductive channel structure which includes a first conductive channel layer including a first conductive channel, and a first and a second doped regions respectively located at two ends of the first conductive channel, a second conductive channel layer including a second conductive channel, and a third and a fourth doped regions respectively located at two ends of the second conductive channel and a conductive buffer layer configured to reduce electrical interference between the first and the third doped regions; a first conductive layer in contact with the second doped region; a second conductive layer nested on the conductive channel structure and in contact with the first and the third doped regions; and a gate structure arranged around the first conductive channel and the second conductive channel.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming a bottom electrode layer on the base, wherein a crystal structure of the bottom electrode layer includes a tetragonal crystal system; forming a first dielectric layer on a surface of the bottom electrode layer by using the bottom electrode layer as a seed layer, wherein a crystal structure of the first dielectric layer includes a tetragonal crystal system; and forming a first current blocking layer on a surface of the first dielectric layer.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.