Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove, an upper surface of the semiconductor die stack being lower than or flush with an upper edge of the groove, and a bottom of the semiconductor die stack being electrically connected to the electrically conductive pillar; and providing an insulating material on the semiconductor die stack to form a semiconductor package structure.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a preset memory space if an error occurs in the data to be read out, and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, and each of the plurality of memory bits is associated with a spare memory cell.

Abstract: A vent filter and a Radio Remote Unit having the vent filter. The vent filter includes a first member including a first body having a ventilation path extending through the first body, an inner wall constituting a ventilation hole which is communicated with the ventilation path, and an outer wall constituting a gap between the inner wall and the outer wall. The vent filter also includes a second member including a second body and at least one enclosure wall protruding out from the second body, wherein at least one of the at least one enclosure wall is located outside the outer wall and surrounding the outer wall. Both the inner and outer walls have at least one first groove at an end and each of the at least one enclosure wall has at least one second groove at an end.

Abstract: Embodiment provides an on-chip reference current generating circuit for supplying at least one reference current to at least one load. The on-chip reference current generating circuit includes a transistor, an operational amplifier unit, a first pull-down resistor unit, and a current mirror unit. A reference voltage is inputted to a positive input terminal of the operational amplifier unit, a negative input terminal of the operational amplifier unit is coupled to a source of the transistor, and an output terminal of the operational amplifier unit is coupled to a gate of the transistor. As a resistor unit calibrated by a ZQ calibration circuit, the first pull-down resistor unit is coupled between the source of the transistor and a ground. The current mirror unit is coupled between a drain of the transistor and a power supply voltage and is configured to output a generated current to the load for use.

Abstract: A vent filter and a Radio Remote Unit having the vent filter. The vent filter includes a first member including a first body having a ventilation path extending through the first body, an inner wall constituting a ventilation hole which is communicated with the ventilation path, and an outer wall constituting a gap between the inner wall and the outer wall. The vent filter also includes a second member including a second body and at least one enclosure wall protruding out from the second body, wherein at least one of the at least one enclosure wall is located outside the outer wall and surrounding the outer wall. Both the inner and outer walls have at least one first groove at an end and each of the at least one enclosure wall has at least one second groove at an end.

Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a substrate and a fin protruding from the substrate, an isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers a part of side walls of the fin; forming a dummy gate structure across the fin, including a dummy gate layer, where the dummy gate structure covers a part of the top and a part of the side walls of the fin; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, where the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate layer and forming an opening in the interlayer dielectric layer; removing partial thickness of the isolation layer exposed by the opening and forming a groove in the isolation layer; and forming a gate structure in the groove and the opening, where the gate structure crosses the fin and covers a part of the top and a part of the side wa

Abstract: Non-volatile memory and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a first conductive layer on the base substrate; forming an interlayer dielectric layer on the first conductive layer; forming a plurality of through holes exposing the first conductive layer in the interlayer dielectric layer; forming a catalyst layer on at least one of sidewall surfaces and bottom surfaces of the through holes; forming a carbon nanotube layer in the through holes by a catalytic chemical vapor deposition process; and forming a second conductive layer on the carbon nanotube layer and a portion of the interlayer dielectric layer.