Patents by Inventor Zhiyuan Ye

Zhiyuan Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10440253
    Abstract: A method and a terminal for focusing includes: a determining step, determining a first camera focus of two camera focuses of two cameras corresponding to a first touch point of two touch points and a second camera focus of the two camera focuses of the two cameras corresponding to a second touch point of the two touch points, respectively, when a shooting preview interface corresponding to the two cameras is displayed and the two touch points are detected on the shooting preview interface; and a focus adjustment step, adjusting position of the first camera focus and the second camera focus, respectively, according to a sliding trace of the first touch point and a sliding trace of the second touch point on the shooting preview interface, in which the first camera focus and the second camera focus are on a same straight line.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Yulong Computer Telecommunications Scientific (Shenzhen) Co., Ltd.
    Inventors: Jian Wang, Zhiyuan Ye
  • Publication number: 20190293476
    Abstract: Mass flow verification systems and apparatus verify mass flow rates of mass flow controllers (MFCs) based on pressure decay principles. Embodiments include a location for coupling a calibrated gas flow standard or a MFC to be tested in a line to receive a gas flow from a gas supply; a control volume serially coupled to the location in the line to receive the gas flow; a flow restrictor serially coupled to the control volume; a pump serially coupled to the flow restrictor; and a controller adapted to allow the gas supply to flow gas through the mass flow control verification system to achieve a stable pressure in the control volume, terminate the gas flow from the gas supply, and measure a rate of pressure decay in the control volume over time. Numerous additional aspects are disclosed.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 26, 2019
    Inventors: Zhiyuan Ye, Justin Hough, Marcel E. Josephson
  • Publication number: 20190267263
    Abstract: Embodiments described herein provide processing chambers that include an enclosure for a processing volume, a rotatable support within the enclosure, the support having a shaft that extends outside the enclosure, wherein the shaft has a signal feature located outside the processing volume, an energy module within the enclosure, wherein the shaft extends through the energy module, one or more directed energy sources coupled to the enclosure, and one or more signalers positioned proximate to the signal feature, each signaler coupled to at least one of the directed energy sources.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 29, 2019
    Inventors: Shu-Kwan Danny LAU, Zhiyuan YE, Zuoming ZHU, Nyi O. MYO, Errol Antonio C. SANCHEZ, Schubert S. CHU
  • Publication number: 20190257000
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support including a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 22, 2019
    Inventors: NYI O. MYO, KEVIN BAUTISTA, ZHIYUAN YE, SCHUBERT S. CHU, YIHWAN KIM
  • Publication number: 20190206707
    Abstract: Methods and gas flow control assemblies configured to deliver gas to process chamber zones in desired flow ratios. In some embodiments, assemblies include one or more MFCs and a back pressure controller (BPC). Assemblies includes a controller, a process gas supply, a distribution manifold, a pressure sensor coupled to the distribution manifold and configured to sense back pressure of the distribution manifold, a process chamber, a one or more mass flow controllers connected between the distribution manifold and process chamber to control gas flow there between, and a back pressure controller provided in fluid parallel relationship to the one or more mass flow controllers, wherein precise flow ratio control is achieved. Alternate embodiments include an upstream pressure controller configured to control flow of carrier gas to control back pressure. Further methods and assemblies for controlling zonal gas flow ratios are described, as are other aspects.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 4, 2019
    Inventors: Kevin Brashear, Ashley M. Okada, Dennis L. Demars, Zhiyuan Ye, Jaidev Rajaram, Marcel E. Josephson
  • Publication number: 20190127851
    Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. The thermal process chamber includes a substrate support, a first plurality of heating elements disposed over or below the substrate support, and a spot heating module disposed over the substrate support. The spot heating module is utilized to provide local heating of cold regions on a substrate disposed on the substrate support during processing. Localized heating of the substrate improves temperature profile, which in turn improves deposition uniformity.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Shu-Kwan LAU, Koji NAKANISHI, Toshiyuki NAKAGAWA, Zuoming ZHU, Zhiyuan YE, Joseph M. RANISH, Nyi O. MYO, Errol Antonio C. SANCHEZ, Schubert S. CHU
  • Patent number: 10276688
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Flora Fong-Song Chang, Abhishek Dube, Xuebin Li, Errol Antonio C. Sanchez, Hua Chung, Schubert S. Chu
  • Publication number: 20190119814
    Abstract: Embodiments of a precursor feed system for a semiconductor process are described herein. The precursor feed system provides improved flow control of a vaporized precursor material to a process chamber by improving flow characteristics of vaporized precursor materials, carried by a carrier gas, which may be an inert gas. The precursor feed system also reduces an occurrence of a pressure drop in conduits that deliver the precursor to the process chamber. Reducing the occurrence of the pressure drop also reduces a decrease of energy from the gas, thus reducing a tendency of the gas to condense in the along the flow path.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Inventors: Zhiyuan YE, Garry KWONG, Errol Antonio C. SANCHEZ, Nyi O. MYO
  • Patent number: 10269600
    Abstract: Methods and gas flow control assemblies configured to deliver gas to process chamber zones in desired flow ratios. In some embodiments, assemblies include one or more MFCs and a back pressure controller (BPC). Assemblies includes a controller, a process gas supply, a distribution manifold, a pressure sensor coupled to the distribution manifold and configured to sense back pressure of the distribution manifold, a process chamber, a one or more mass flow controllers connected between the distribution manifold and process chamber to control gas flow there between, and a back pressure controller provided in fluid parallel relationship to the one or more mass flow controllers, wherein precise flow ratio control is achieved. Alternate embodiment include an upstream pressure controller configured to control flow of carrier gas to control back pressure. Further methods and assemblies for controlling zonal gas flow ratios are described, as are other aspects.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 23, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Brashear, Ashley M. Okada, Dennis L. Demars, Zhiyuan Ye, Jaidev Rajaram, Marcel E. Josephson
  • Patent number: 10260164
    Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support comprising a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 16, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nyi O. Myo, Kevin Bautista, Zhiyuan Ye, Schubert S. Chu, Yihwan Kim
  • Patent number: 10256322
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 9, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Hua Chung
  • Patent number: 10224421
    Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Xinyu Bao, Chun Yan, Hua Chung, Schubert S. Chu, Satheesh Kuppurao
  • Publication number: 20180366363
    Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Anhthu NGO, Zuoming ZHU, Balasubramanian RAMACHANDRAN, Paul BRILLHART, Edric TONG, Anzhong CHANG, Kin Pong LO, Kartik SHAH, Schubert S. CHU, Zhepeng CONG, James Francis MACK, Nyi O. MYO, Kevin Joseph BAUTISTA, Xuebin LI, Yi-Chiau HUANG, Zhiyuan YE
  • Patent number: 10132003
    Abstract: Embodiments disclosed herein generally related to a processing chamber, and more specifically a heat modulator assembly for use in a processing chamber. The heat modulator assembly includes a heat modulator housing and a plurality of heat modulators. The heat modulator housing includes a housing member defining a housing plane, a sidewall, and an annular extension. The sidewall extends perpendicular to the housing plane. The annular extension extends outward from the sidewall. The plurality of heat modulators is positioned in the housing member.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 20, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shu-Kwan Lau, Surajit Kumar, Joseph M. Ranish, Zhiyuan Ye, Kartik Shah, Mehmet Tugrul Samir, Errol Antonio C. Sanchez
  • Patent number: 10125415
    Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Errol Antonio C. Sanchez, Keun-Yong Ban, Xinyu Bao
  • Publication number: 20180286961
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Application
    Filed: February 14, 2018
    Publication date: October 4, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Flora Fong-Song CHANG, Abhishek DUBE, Xuebin LI, Errol Antonio C. SANCHEZ, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180286962
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Application
    Filed: March 20, 2018
    Publication date: October 4, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Hua CHUNG
  • Publication number: 20180277649
    Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 27, 2018
    Inventors: Zhiyuan YE, Xinyu BAO, Chun YAN, Hua CHUNG, Schubert S. CHU, Satheesh KUPPURAO
  • Publication number: 20180261454
    Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.
    Type: Application
    Filed: June 27, 2016
    Publication date: September 13, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
  • Patent number: 10062598
    Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 28, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Anhthu Ngo, Zuoming Zhu, Balasubramanian Ramachandran, Paul Brillhart, Edric Tong, Anzhong Chang, Kin Pong Lo, Kartik Shah, Schubert S. Chu, Zhepeng Cong, James Francis Mack, Nyi O. Myo, Kevin Joseph Bautista, Xuebin Li, Yi-Chiau Huang, Zhiyuan Ye