Abstract: Methods and gas flow control assemblies configured to deliver gas to process chamber zones in desired flow ratios. In some embodiments, assemblies include one or more MFCs and a back pressure controller (BPC). Assemblies includes a controller, a process gas supply, a distribution manifold, pressure sensor coupled to the distribution manifold and configured to sense back pressure of the distribution manifold, a process chamber, a one or more mass flow controllers connected between the distribution manifold and process chamber to control gas flow there between, and a back pressure controller provided in fluid parallel relationship to the one or more mass flow controllers, wherein precise flow ratio control is achieved. Alternate embodiment include an upstream pressure controller configured to control flow of carrier gas to control back pressure. Further methods and assemblies for controlling zonal gas flow ratios are described, as are other aspects.

Abstract: Methods and gas flow control assemblies configured to deliver gas to process chamber zones in desired flow ratios. In some embodiments, assemblies include one or more MFCs and a back pressure controller (BPC). Assemblies includes a controller, a process gas supply, a distribution manifold, a pressure sensor coupled to the distribution manifold and configured to sense back pressure of the distribution manifold, a process chamber, a one or more mass flow controllers connected between the distribution manifold and process chamber to control gas flow there between, and a back pressure controller provided in fluid parallel relationship to the one or more mass flow controllers, wherein precise flow ratio control is achieved. Alternate embodiments include an upstream pressure controller configured to control flow of carrier gas to control back pressure. Further methods and assemblies for controlling zonal gas flow ratios are described, as are other aspects.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

Abstract: The present disclosure generally relate to methods for forming an epitaxial layer on a semiconductor device, including a method of forming a tensile-stressed germanium arsenic layer. The method includes heating a substrate disposed within a processing chamber, wherein the substrate comprises silicon, and exposing a surface of the substrate to a germanium-containing gas and an arsenic-containing gas to form a germanium arsenic alloy having an arsenic concentration of 4.5×1020 atoms per cubic centimeter or greater on the surface.

Abstract: Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support comprising a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed.

Abstract: A method and a terminal for focusing includes: a determining step, determining a first camera focus of two camera focuses of two cameras corresponding to a first touch point of two touch points and a second camera focus of the two camera focuses of the two cameras corresponding to a second touch point of the two touch points, respectively, when a shooting preview interface corresponding to the two cameras is displayed and the two touch points are detected on the shooting preview interface; and a focus adjustment step, adjusting position of the first camera focus and the second camera focus, respectively, according to a sliding trace of the first touch point and a sliding trace of the second touch point on the shooting preview interface, in which the first camera focus and the second camera focus are on a same straight line.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. The thermal process chamber may include a substrate support, a first plurality of heating elements disposed over the substrate support, and one or more high-energy radiant source assemblies disposed over the first plurality of heating elements. The one or more high-energy radiant source assemblies are utilized to provide local heating of cold regions on a substrate disposed on the substrate support during processing. Localized heating of the substrate improves temperature profile, which in turn improves deposition uniformity.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.

Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.

Abstract: Embodiments provided herein generally relate to an apparatus for gas delivering in a semiconductor process chamber. The apparatus may be a gas distribution plate that has a plurality of through holes and a plurality of blind holes formed therein. Process gases are provided into a processing volume of the semiconductor process chamber through the through holes of the gas distribution plate. The blind holes are utilized to control the temperature of the gas distribution plate using a phase change material.

Abstract: Embodiments of the disclosure relate to a perimeter pumping member for a processing chamber. The perimeter pumping member comprises a ring-shaped body having a first curved channel along an arc within the ring-shaped body, a first inner channel connecting a first region of the first curved channel to a first region of an inner surface of the ring-shaped body, a plurality of second inner channels connecting a second region of the first curved channel to a second region of the inner surface, and a first outer channel connecting the first region of the first curved channel to an outer surface of the ring-shaped body, wherein the second inner channels are each sized such that, when a fluid is pumped out of the perimeter pumping member via the first outer channel, the fluid flows through the first inner channel and the second inner channels at a uniform flow rate.

Abstract: Methods and apparatus for gas delivery are disclosed herein. In some embodiments, a gas delivery system includes an ampoule for storing a precursor in solid or liquid form, a first conduit coupled to the ampoule and having a first end coupled to a first gas source to draw a vapor of the precursor from the ampoule into the first conduit, a second conduit coupled to the first conduit at a first junction located downstream of the ampoule and having a first end coupled to a second gas source and a second end coupled to a process chamber, and a heat source configured to heat the ampoule and at least a first portion of the first conduit from the ampoule to the second conduit and to heat only a second portion of the second conduit, wherein the second portion of the second conduit includes the first junction.

Abstract: Embodiments disclosed herein relate to a light pipe structure for thermal processing of semiconductor substrates. In one embodiment, a light pipe window structure for use in a thermal process chamber includes a transparent plate, and a plurality of light pipe structures formed in a transparent material that is coupled to the transparent plate, each of the plurality of light pipe structures comprising a reflective surface and having a longitudinal axis disposed in a substantially perpendicular relation to a plane of the transparent plate.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.