Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

Abstract: Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Abstract: The present invention provides constructs of the parainfluenza virus type-5 (PIV5) virus expressing the SARS-CoV-2 envelope spike (S) and nucleocapsid (N) proteins of SARS-CoV-2 variants for use as safe, stable, efficacious, and cost-effective vaccines against COVID-19.

Abstract: Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Abstract: A preparation method of a granular adsorbent is provided, including the following: adding a pyrrole monomer to an acidic solution, and adding an oxidant as an initiator to allow a polymerization reaction of the pyrrole monomer to produce polypyrrole (PPy), where an adsorption material powder is added to a reaction system before, during, or immediately after the polymerization reaction, and a resulting mixture is thoroughly stirred; after the polymerization reaction is completed, filtering a resulting reaction system to obtain a filter cake, which is the granular adsorbent; or subjecting the resulting reaction system to centrifugal sedimentation to obtain the monolithic adsorbent. In the present disclosure, the pyrrole monomer is subjected to a polymerization reaction to generate PPy; before being tightly stacked, network structures of PPy wrap the adsorption material powder; and the granular adsorbent is formed through sedimentation and stacking.

Abstract: A pose tracking method and apparatus are disclosed. The pose tracking method includes obtaining an image of a trackable target having a plurality of markers, detecting first points in the obtained image to which the markers are projected, matching the first points and second points corresponding to positions of the markers in a coordinate system set based on the trackable target based on rotation information of the trackable target, and estimating a pose of the trackable target based on matching pairs of the first points and the second points.

Abstract: In some embodiments, an electronic device presents a weak password warning in a password management user interface that includes information about the user account with which the password is associated. In some embodiments, an electronic device presents a weak password warning in a login user interface.

Abstract: A switch control circuit a multiplexer switch circuit and a control method for a multiplexer switch control circuit are provided. The switch control circuit comprises a first control switch, a first capacitor and a field-effect transistor switch. When the first control switch is switched off, a charging voltage released by the first capacitor can control the switching-on of the field-effect transistor switch. At this moment, since the first control switch is switched off, and a power source signal cannot reach a gate electrode of the field-effect transistor switch, power source noise cannot be coupled to a line where source and drain electrodes of the field-effect transistor switch are located. Thus, in a discharge stage of the first capacitor, a discharge voltage can serve as a control signal to control the switching-on of the field-effect transistor switch.

Abstract: A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Abstract: A data processing method and device, and a computer readable storage medium, the data processing method, applied to a node in an Information-Centric Network (ICN), includes: acquiring a first offset address corresponding to a first ICN packet; querying a record pointed to by the first offset address and performing data processing according to a query result; the record pointed to by the first offset address is used to store a storage address of a second ICN packet or forwarding information of the second ICN packet in response to the second ICN packet corresponding to the first ICN packet being stored locally.

Abstract: A pose estimation method includes obtains an event stream from an event-based vision sensor configured to capture a target object to which light-emitting devices flickering at a predetermined first frequency are attached, obtains a polarity change period of at least one pixel based on the event stream, generates an image frame sequence using at least one target pixel having a polarity change period corresponding to the first frequency, among the at least one pixel, extracts a feature sequence including feature vectors corresponding to the at least one target pixel, from the image frame sequence, and estimates a pose sequence of the target object by applying the feature sequence to a deep neural network (DNN) model.

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: A method and apparatus for processing sparse points. The method includes determining spatial hierarchical point data based on a key point set and a local point set of a sparse point set, determining relationship feature data by encoding a spatial hierarchical relationship between points of the spatial hierarchical point data, generating a global feature and a local feature of the sparse point set through a conversion operation associated with the relationship feature data, and generating a processing result for the sparse point set based on the global feature and the local feature.

Abstract: An electronic device: displays an electronic form with a plurality of fields; detects an autofill input that corresponds to a field of the plurality of fields in the electronic form; and in response to detecting the autofill input, updates the electronic form to display fields that have been populated based on a user profile. If the autofill input is associated with a first category of information in the user profile, updating the electronic form includes populating at least two of the plurality of fields using information from the user profile that corresponds to the first category of information. If the autofill input is associated with a second category of information in the user profile, updating the electronic form includes populating at least two of the plurality of fields using information from the user profile that corresponds to the second category of information.

Abstract: A display substrate, a display panel and a method for manufacturing the display substrate are provided. The display substrate comprises a backing substrate and a plurality of pixel areas formed on the backing substrate, wherein the display substrate further comprises a quantum dot layer, the quantum dot layer comprises a plurality of quantum dot units located in the plurality of pixel areas respectively, wherein the quantum dot units comprise a matrix layer and quantum dots dispersed in the matrix layer, the matrix layer comprises a central region and a peripheral region disposed around the central region, the peripheral region comprises a polymer of photocurable monomers, and the central region comprises unpolymerized photocurable monomers.