Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Abstract: Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.

Abstract: A pose tracking method and apparatus are disclosed. The pose tracking method includes obtaining an image of a trackable target having a plurality of markers, detecting first points in the obtained image to which the markers are projected, matching the first points and second points corresponding to positions of the markers in a coordinate system set based on the trackable target based on rotation information of the trackable target, and estimating a pose of the trackable target based on matching pairs of the first points and the second points.

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

Abstract: A system and method for providing an autonomous delivery vehicle (ADV) incorporated with intelligent ramp control is disclosed. The ADV is configured to make decisions to deploy/retract the ramps depending on some conditions around the ADV. The ADV comprising a computing device including a means for executing artificial intelligence (AI) software, a ramp system comprising a plurality of ramps, and a sensor assembly in communication with the computing device to collect environmental data around the ADV. The data is communicated to the AI software, which is configured to analyze the environmental data to detect one or more obstacles proximate to the plurality of ramps of the ADV. Further, AI software determines a decision to deploy/retract at least one ramp based on the analysis and transmits the decision to the computing device. The computing device is configured to manipulate each ramp to deploy/retract based on the received decision.

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

Abstract: Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.

Abstract: An array substrate, a liquid crystal display panel and a display device are provided. The array substrate includes: a substrate; a common electrode and a gate electrode, both disposed on the substrate; and a shielding electrode, disposed on the common electrode and the gate electrode, wherein an orthographic projection of the shielding electrode on the substrate is overlapped with an orthographic projection of the gate electrode on the substrate as well as an orthographic projection of the common electrode on the substrate, and the shielding electrode is electrically connected to the common electrode. In the embodiment of the disclosure, the shielding electrode is disposed on the common electrode and the gate electrode, so that the influence of the voltage difference formed by the gate electrode and the common electrode can be effectively shielded, thereby eliminating the phenomenon of push mura.

Abstract: Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.

Abstract: A pose estimation method includes obtains an event stream from an event-based vision sensor configured to capture a target object to which light-emitting devices flickering at a predetermined first frequency are attached, obtains a polarity change period of at least one pixel based on the event stream, generates an image frame sequence using at least one target pixel having a polarity change period corresponding to the first frequency, among the at least one pixel, extracts a feature sequence including feature vectors corresponding to the at least one target pixel, from the image frame sequence, and estimates a pose sequence of the target object by applying the feature sequence to a deep neural network (DNN) model.

Abstract: A server receives a request for a business account with the messaging system that includes a business name and a contact point. The server determines whether users of the messaging system associate the business name with the contact point. The server also determines whether the business name and/or the contact point has characteristics consistent with the request originating from a genuine business. The business account is validated if users of the messaging system associate the business name with the contact point and at least one of the business name or the contact point have characteristics consistent with the request originating from a genuine business. The business account profile is updated to indicate it is verified. Client devices are adapted to display messages from the business account in conjunction with a visual indicator that the business account is verified.

Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

Abstract: Electronic design automation systems, methods, and media are presented for slack scheduling. Some embodiments analyzing slack values at the input and output of a circuit element across multiple views. A skew value is then selected which maximizes the slack at the input and output of the circuit element across all views. In some embodiments, this selection operation is streamlined by first identifying skew ranges that preserve a local worst negative slack, and the selected skew value to maximize the slacks is chosen from the identified skew ranges, in order to limit the computational resources in identifying the skew which maximizes the minimum slack value. An updated circuit design and associated circuitry may then be generated.

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Abstract: In some embodiments, an electronic device presents a weak password warning in a password management user interface that includes information about the user account with which the password is associated. In some embodiments, an electronic device presents a weak password warning in a login user interface.